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Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y')
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27235 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -212,6 +212,7 @@ namespace {
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SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
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SDOperand visitINSERT_VECTOR_ELT(SDNode *N);
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SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
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SDOperand visitVINSERT_VECTOR_ELT(SDNode *N);
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SDOperand visitVBUILD_VECTOR(SDNode *N);
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SDOperand visitVBUILD_VECTOR(SDNode *N);
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SDOperand visitVECTOR_SHUFFLE(SDNode *N);
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SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
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SDOperand ReassociateOps(unsigned Opc, SDOperand LHS, SDOperand RHS);
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@ -646,6 +647,7 @@ SDOperand DAGCombiner::visit(SDNode *N) {
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case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
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case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N);
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case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
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case ISD::VINSERT_VECTOR_ELT: return visitVINSERT_VECTOR_ELT(N);
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case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
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case ISD::VBUILD_VECTOR: return visitVBUILD_VECTOR(N);
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case ISD::VECTOR_SHUFFLE: return visitVECTOR_SHUFFLE(N);
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}
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}
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return SDOperand();
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return SDOperand();
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}
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}
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@ -2427,6 +2429,34 @@ SDOperand DAGCombiner::visitVBUILD_VECTOR(SDNode *N) {
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return SDOperand();
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return SDOperand();
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}
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}
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SDOperand DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
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// If the LHS and the RHS are the same node, turn the RHS into an undef.
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if (N->getOperand(0) == N->getOperand(1)) {
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// Check the SHUFFLE mask, mapping any inputs from the 2nd operand into the
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// first operand.
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std::vector<SDOperand> MappedOps;
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SDOperand ShufMask = N->getOperand(2);
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unsigned NumElts = ShufMask.getNumOperands();
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for (unsigned i = 0, e = ShufMask.getNumOperands(); i != e; ++i) {
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if (cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() >= NumElts) {
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unsigned NewIdx =
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cast<ConstantSDNode>(ShufMask.getOperand(i))->getValue() - NumElts;
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MappedOps.push_back(DAG.getConstant(NewIdx, MVT::i32));
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} else {
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MappedOps.push_back(ShufMask.getOperand(i));
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}
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}
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ShufMask = DAG.getNode(ISD::BUILD_VECTOR, ShufMask.getValueType(),
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MappedOps);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, N->getValueType(0),
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N->getOperand(0),
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DAG.getNode(ISD::UNDEF, N->getValueType(0)),
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ShufMask);
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}
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return SDOperand();
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}
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SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
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SDOperand DAGCombiner::SimplifySelect(SDOperand N0, SDOperand N1, SDOperand N2){
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assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
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assert(N0.getOpcode() ==ISD::SETCC && "First argument must be a SetCC node!");
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