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https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-16 14:31:59 +00:00
Changed definition of EXT and INS per Bruno's comments.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@137892 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -558,8 +558,8 @@ static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG,
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return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32,
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ShiftRight.getOperand(0),
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DAG.getConstant(SMSize, MVT::i32),
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DAG.getConstant(Pos, MVT::i32));
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DAG.getConstant(Pos, MVT::i32),
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DAG.getConstant(SMSize, MVT::i32));
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}
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static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
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@ -613,8 +613,8 @@ static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG,
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return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32,
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Shl.getOperand(0),
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DAG.getConstant(SMSize0, MVT::i32),
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DAG.getConstant(SMPos0, MVT::i32),
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DAG.getConstant(SMSize0, MVT::i32),
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And0.getOperand(0));
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}
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@ -102,28 +102,6 @@ class FJ<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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let Inst{25-0} = addr;
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}
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// Ext and Ins
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class ExtIns<bits<6> _funct, string instr_asm, dag Outs, dag Ins,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst<Outs, Ins, !strconcat(instr_asm, "\t$dst, $src, $pos, $size"),
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pattern, itin>
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{
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bits<5> rt;
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bits<5> rs;
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bits<5> sz;
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bits<5> pos;
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bits<6> funct;
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let opcode = 0x1f;
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let funct = _funct;
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let Inst{25-21} = rs;
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let Inst{20-16} = rt;
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let Inst{15-11} = sz;
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let Inst{10-6} = pos;
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let Inst{5-0} = funct;
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}
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//===----------------------------------------------------------------------===//
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//
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// FLOATING POINT INSTRUCTION FORMATS
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@ -405,6 +405,19 @@ class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src),
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let shamt = 0;
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}
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// Ext and Ins
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class ExtIns<bits<6> _funct, string instr_asm, dag ins,
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list<dag> pattern, InstrItinClass itin>:
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FR<0x1f, _funct, (outs CPURegs:$rt), ins,
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!strconcat(instr_asm, "\t$rt, $rs, $pos, $size"), pattern, itin> {
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bits<5> src;
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bits<5> pos;
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bits<5> size;
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let rs = src;
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let rd = size;
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let shamt = pos;
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}
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// Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
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class Atomic2Ops<PatFrag Op, string Opstr> :
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MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
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@ -677,20 +690,19 @@ def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>;
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def RDHWR : ReadHardware;
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let Predicates = [IsMips32r2] in {
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def Ext : ExtIns<0b000000, "ext", (outs CPURegs:$dst),
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(ins CPURegs:$src, uimm16:$size, uimm16:$pos),
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[(set CPURegs:$dst,
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(MipsExt CPURegs:$src, immZExt5:$size, immZExt5:$pos))],
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NoItinerary>;
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let Constraints = "$src1 = $dst" in
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def Ins : ExtIns<0b000100, "ins",
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(outs CPURegs:$dst),
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(ins CPURegs:$src, uimm16:$size, uimm16:$pos,
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CPURegs:$src1),
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[(set CPURegs:$dst,
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(MipsIns CPURegs:$src, immZExt5:$size, immZExt5:$pos,
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CPURegs:$src1))],
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NoItinerary>;
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def EXT : ExtIns<0, "ext", (ins CPURegs:$rs, uimm16:$pos, uimm16:$size),
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[(set CPURegs:$rt,
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(MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$size))],
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NoItinerary>;
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let Constraints = "$src = $rt" in
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def INS : ExtIns<4, "ins",
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(ins CPURegs:$rs, uimm16:$pos, uimm16:$size, CPURegs:$src),
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[(set CPURegs:$rt,
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(MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$size,
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CPURegs:$src))],
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NoItinerary>;
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}
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//===----------------------------------------------------------------------===//
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