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Small cleanups in the PowerPC backend.

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Small refactoring in LowerFORMAL_ARGUMENTS().
Correct minor formatting issues.
Remove size argument of CreateCopyOfByValArgument().
Remove dead argument from CalculateStackSlotSize().
Remove unused variable ReturnAddrIndex from various targets.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74763 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tilmann Scheller
2009-07-03 06:43:35 +00:00
parent 0b1308f189
commit 667ee3cb43
4 changed files with 21 additions and 38 deletions
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1
lib/Target/CellSPU/SPUISelLowering.h
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@@ -89,7 +89,6 @@ namespace llvm {
public TargetLowering public TargetLowering
{ {
int VarArgsFrameIndex; // FrameIndex for start of varargs area. int VarArgsFrameIndex; // FrameIndex for start of varargs area.
int ReturnAddrIndex; // FrameIndex for return slot.
SPUTargetMachine &SPUTM; SPUTargetMachine &SPUTM;
public: public:

2
lib/Target/Mips/MipsISelLowering.h
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@@ -68,8 +68,6 @@ namespace llvm {
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
class MipsTargetLowering : public TargetLowering class MipsTargetLowering : public TargetLowering
{ {
// FrameIndex for return slot.
int ReturnAddrIndex;
public: public:
explicit MipsTargetLowering(MipsTargetMachine &TM); explicit MipsTargetLowering(MipsTargetMachine &TM);

55
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@@ -1387,9 +1387,9 @@ static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
/// CalculateStackSlotSize - Calculates the size reserved for this argument on /// CalculateStackSlotSize - Calculates the size reserved for this argument on
/// the stack. /// the stack.
static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags, static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags,
bool isVarArg, unsigned PtrByteSize) { unsigned PtrByteSize) {
MVT ArgVT = Arg.getValueType(); MVT ArgVT = Arg.getValueType();
unsigned ArgSize =ArgVT.getSizeInBits()/8; unsigned ArgSize = ArgVT.getSizeInBits()/8;
if (Flags.isByVal()) if (Flags.isByVal())
ArgSize = Flags.getByValSize(); ArgSize = Flags.getByValSize();
ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize; ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
@@ -1409,7 +1409,6 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
// //
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo(); MachineFrameInfo *MFI = MF.getFrameInfo();
MachineRegisterInfo &RegInfo = MF.getRegInfo();
SmallVector<SDValue, 8> ArgValues; SmallVector<SDValue, 8> ArgValues;
SDValue Root = Op.getOperand(0); SDValue Root = Op.getOperand(0);
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0; bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
@@ -1534,14 +1533,12 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
MinReservedArea = ((MinReservedArea+15)/16)*16; MinReservedArea = ((MinReservedArea+15)/16)*16;
MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo), MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
Flags, Flags,
isVarArg,
PtrByteSize); PtrByteSize);
} else nAltivecParamsAtEnd++; } else nAltivecParamsAtEnd++;
} else } else
// Calculate min reserved area. // Calculate min reserved area.
MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo), MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
Flags, Flags,
isVarArg,
PtrByteSize); PtrByteSize);
// FIXME alignment for ELF may not be right // FIXME alignment for ELF may not be right
@@ -1564,8 +1561,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
ArgValues.push_back(FIN); ArgValues.push_back(FIN);
if (ObjSize==1 || ObjSize==2) { if (ObjSize==1 || ObjSize==2) {
if (GPR_idx != Num_GPR_Regs) { if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN, SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 ); NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
@@ -1582,8 +1578,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
// to memory. ArgVal will be address of the beginning of // to memory. ArgVal will be address of the beginning of
// the object. // the object.
if (GPR_idx != Num_GPR_Regs) { if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset); int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT); SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
@@ -1607,8 +1602,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2); if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
if (GPR_idx != Num_GPR_Regs) { if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32); ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
++GPR_idx; ++GPR_idx;
} else { } else {
@@ -1625,8 +1619,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
// FALLTHROUGH // FALLTHROUGH
case MVT::i64: // PPC64 case MVT::i64: // PPC64
if (GPR_idx != Num_GPR_Regs) { if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64); ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
if (ObjectVT == MVT::i32) { if (ObjectVT == MVT::i32) {
@@ -1662,11 +1655,12 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
} }
if (FPR_idx != Num_FPR_Regs) { if (FPR_idx != Num_FPR_Regs) {
unsigned VReg; unsigned VReg;
if (ObjectVT == MVT::f32) if (ObjectVT == MVT::f32)
VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass); VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
else else
VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass); VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
RegInfo.addLiveIn(FPR[FPR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
++FPR_idx; ++FPR_idx;
} else { } else {
@@ -1686,8 +1680,7 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
// Note that vector arguments in registers don't reserve stack space, // Note that vector arguments in registers don't reserve stack space,
// except in varargs functions. // except in varargs functions.
if (VR_idx != Num_VR_Regs) { if (VR_idx != Num_VR_Regs) {
unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass); unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
RegInfo.addLiveIn(VR[VR_idx], VReg);
ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT); ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
if (isVarArg) { if (isVarArg) {
while ((ArgOffset % 16) != 0) { while ((ArgOffset % 16) != 0) {
@@ -1791,12 +1784,12 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
// result of va_next. // result of va_next.
for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) { for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
unsigned VReg; unsigned VReg;
if (isPPC64) if (isPPC64)
VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass); VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
else else
VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass); VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
RegInfo.addLiveIn(GPR[GPR_idx], VReg);
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT); SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store); MemOps.push_back(Store);
@@ -1819,10 +1812,8 @@ PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
} }
for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) { for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
unsigned VReg; unsigned VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
RegInfo.addLiveIn(FPR[FPR_idx], VReg);
SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64); SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0); SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
MemOps.push_back(Store); MemOps.push_back(Store);
@@ -1885,7 +1876,7 @@ CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
// Varargs and 64-bit Altivec parameters are padded to 16 byte boundary. // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
NumBytes = ((NumBytes+15)/16)*16; NumBytes = ((NumBytes+15)/16)*16;
} }
NumBytes += CalculateStackSlotSize(Arg, Flags, isVarArg, PtrByteSize); NumBytes += CalculateStackSlotSize(Arg, Flags, PtrByteSize);
} }
// Allow for Altivec parameters at the end, if needed. // Allow for Altivec parameters at the end, if needed.
@@ -2096,8 +2087,8 @@ SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
static SDValue static SDValue
CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
ISD::ArgFlagsTy Flags, SelectionDAG &DAG, ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
unsigned Size, DebugLoc dl) { DebugLoc dl) {
SDValue SizeNode = DAG.getConstant(Size, MVT::i32); SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
false, NULL, 0, NULL, 0); false, NULL, 0, NULL, 0);
} }
@@ -2150,10 +2141,6 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
MachineFunction &MF = DAG.getMachineFunction(); MachineFunction &MF = DAG.getMachineFunction();
// args_to_use will accumulate outgoing args for the PPCISD::CALL case in
// SelectExpr to use to put the arguments in the appropriate registers.
std::vector<SDValue> args_to_use;
// Mark this function as potentially containing a function that contains a // Mark this function as potentially containing a function that contains a
// tail call. As a consequence the frame pointer will be used for dynamicalloc // tail call. As a consequence the frame pointer will be used for dynamicalloc
// and restoring the callers stack pointer in this functions epilog. This is // and restoring the callers stack pointer in this functions epilog. This is
@@ -2217,7 +2204,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
}; };
const unsigned NumGPRs = array_lengthof(GPR_32); const unsigned NumGPRs = array_lengthof(GPR_32);
const unsigned NumFPRs = isMachoABI ? 13 : 8; const unsigned NumFPRs = isMachoABI ? 13 : 8;
const unsigned NumVRs = array_lengthof( VR); const unsigned NumVRs = array_lengthof(VR);
const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32; const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
@@ -2273,7 +2260,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr, SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
CallSeqStart.getNode()->getOperand(0), CallSeqStart.getNode()->getOperand(0),
Flags, DAG, Size, dl); Flags, DAG, dl);
// This must go outside the CALLSEQ_START..END. // This must go outside the CALLSEQ_START..END.
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
CallSeqStart.getNode()->getOperand(1)); CallSeqStart.getNode()->getOperand(1));
@@ -2289,7 +2276,7 @@ SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
// registers. (This is not what the doc says.) // registers. (This is not what the doc says.)
SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff, SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
CallSeqStart.getNode()->getOperand(0), CallSeqStart.getNode()->getOperand(0),
Flags, DAG, Size, dl); Flags, DAG, dl);
// This must go outside the CALLSEQ_START..END. // This must go outside the CALLSEQ_START..END.
SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall, SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
CallSeqStart.getNode()->getOperand(1)); CallSeqStart.getNode()->getOperand(1));

1
lib/Target/PowerPC/PPCISelLowering.h
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@@ -223,7 +223,6 @@ namespace llvm {
// register for parameter passing. // register for parameter passing.
unsigned VarArgsNumFPR; // Index of the first unused double unsigned VarArgsNumFPR; // Index of the first unused double
// register for parameter passing. // register for parameter passing.
int ReturnAddrIndex; // FrameIndex for return slot.
const PPCSubtarget &PPCSubTarget; const PPCSubtarget &PPCSubTarget;
public: public:
explicit PPCTargetLowering(PPCTargetMachine &TM); explicit PPCTargetLowering(PPCTargetMachine &TM);