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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-30 17:33:24 +00:00
ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.
No functional change intended. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144122 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chad Rosier
parent
7781ae5be5
commit
66dc8ca04b
@ -90,7 +90,7 @@ class ARMFastISel : public FastISel {
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ARMFunctionInfo *AFI;
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// Convenience variables to avoid some queries.
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bool isThumb;
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bool isThumb2;
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LLVMContext *Context;
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public:
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@ -101,7 +101,7 @@ class ARMFastISel : public FastISel {
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TLI(*TM.getTargetLowering()) {
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Subtarget = &TM.getSubtarget<ARMSubtarget>();
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AFI = funcInfo.MF->getInfo<ARMFunctionInfo>();
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isThumb = AFI->isThumbFunction();
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isThumb2 = AFI->isThumbFunction();
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Context = &funcInfo.Fn->getContext();
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}
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@ -553,7 +553,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
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const ConstantInt *CI = cast<ConstantInt>(C);
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if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) {
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EVT SrcVT = MVT::i32;
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unsigned Opc = isThumb ? ARM::t2MOVi16 : ARM::MOVi16;
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unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16;
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unsigned ImmReg = createResultReg(TLI.getRegClassFor(SrcVT));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), ImmReg)
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@ -575,7 +575,7 @@ unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, EVT VT) {
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}
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unsigned Idx = MCP.getConstantPoolIndex(C, Align);
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if (isThumb)
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if (isThumb2)
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::t2LDRpci), DestReg)
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.addConstantPoolIndex(Idx));
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@ -596,7 +596,7 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
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Reloc::Model RelocM = TM.getRelocationModel();
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// TODO: Need more magic for ARM PIC.
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if (!isThumb && (RelocM == Reloc::PIC_)) return 0;
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if (!isThumb2 && (RelocM == Reloc::PIC_)) return 0;
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// MachineConstantPool wants an explicit alignment.
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unsigned Align = TD.getPrefTypeAlignment(GV->getType());
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@ -616,7 +616,7 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
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// Load value.
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MachineInstrBuilder MIB;
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unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
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if (isThumb) {
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if (isThumb2) {
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unsigned Opc = (RelocM != Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg)
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.addConstantPoolIndex(Idx);
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@ -633,7 +633,7 @@ unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, EVT VT) {
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if (Subtarget->GVIsIndirectSymbol(GV, RelocM)) {
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unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT));
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if (isThumb)
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if (isThumb2)
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(ARM::t2LDRi12), NewDestReg)
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.addReg(DestReg)
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@ -681,7 +681,7 @@ unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) {
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if (SI != FuncInfo.StaticAllocaMap.end()) {
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TargetRegisterClass* RC = TLI.getRegClassFor(VT);
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unsigned ResultReg = createResultReg(RC);
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unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
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unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addFrameIndex(SI->second)
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@ -864,10 +864,10 @@ void ARMFastISel::ARMSimplifyAddress(Address &Addr, EVT VT) {
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// put the alloca address into a register, set the base type back to
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// register and continue. This should almost never happen.
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if (needsLowering && Addr.BaseType == Address::FrameIndexBase) {
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TargetRegisterClass *RC = isThumb ? ARM::tGPRRegisterClass :
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TargetRegisterClass *RC = isThumb2 ? ARM::tGPRRegisterClass :
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ARM::GPRRegisterClass;
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unsigned ResultReg = createResultReg(RC);
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unsigned Opc = isThumb ? ARM::t2ADDri : ARM::ADDri;
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unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, *FuncInfo.InsertPt, DL,
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TII.get(Opc), ResultReg)
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.addFrameIndex(Addr.Base.FI)
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@ -908,7 +908,7 @@ void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
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MIB.addFrameIndex(FI);
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// ARM halfword load/stores need an additional operand.
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if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
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if (!isThumb2 && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
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MIB.addImm(Addr.Offset);
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MIB.addMemOperand(MMO);
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@ -917,7 +917,7 @@ void ARMFastISel::AddLoadStoreOperands(EVT VT, Address &Addr,
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MIB.addReg(Addr.Base.Reg);
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// ARM halfword load/stores need an additional operand.
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if (!isThumb && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
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if (!isThumb2 && VT.getSimpleVT().SimpleTy == MVT::i16) MIB.addReg(0);
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MIB.addImm(Addr.Offset);
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}
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@ -933,15 +933,15 @@ bool ARMFastISel::ARMEmitLoad(EVT VT, unsigned &ResultReg, Address &Addr) {
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// This is mostly going to be Neon/vector support.
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default: return false;
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case MVT::i16:
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Opc = isThumb ? ARM::t2LDRHi12 : ARM::LDRH;
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Opc = isThumb2 ? ARM::t2LDRHi12 : ARM::LDRH;
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RC = ARM::GPRRegisterClass;
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break;
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case MVT::i8:
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Opc = isThumb ? ARM::t2LDRBi12 : ARM::LDRBi12;
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Opc = isThumb2 ? ARM::t2LDRBi12 : ARM::LDRBi12;
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RC = ARM::GPRRegisterClass;
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break;
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case MVT::i32:
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Opc = isThumb ? ARM::t2LDRi12 : ARM::LDRi12;
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Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12;
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RC = ARM::GPRRegisterClass;
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break;
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case MVT::f32:
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@ -990,22 +990,22 @@ bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr) {
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// This is mostly going to be Neon/vector support.
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default: return false;
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case MVT::i1: {
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unsigned Res = createResultReg(isThumb ? ARM::tGPRRegisterClass :
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unsigned Res = createResultReg(isThumb2 ? ARM::tGPRRegisterClass :
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ARM::GPRRegisterClass);
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unsigned Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
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unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(Opc), Res)
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.addReg(SrcReg).addImm(1));
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SrcReg = Res;
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} // Fallthrough here.
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case MVT::i8:
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StrOpc = isThumb ? ARM::t2STRBi12 : ARM::STRBi12;
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StrOpc = isThumb2 ? ARM::t2STRBi12 : ARM::STRBi12;
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break;
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case MVT::i16:
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StrOpc = isThumb ? ARM::t2STRHi12 : ARM::STRH;
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StrOpc = isThumb2 ? ARM::t2STRHi12 : ARM::STRH;
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break;
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case MVT::i32:
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StrOpc = isThumb ? ARM::t2STRi12 : ARM::STRi12;
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StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12;
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break;
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case MVT::f32:
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if (!Subtarget->hasVFP2()) return false;
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@ -1129,7 +1129,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
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if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned()))
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return false;
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unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
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unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
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.addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
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FastEmitBranch(FBB, DL);
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@ -1140,7 +1140,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
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MVT SourceVT;
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if (TI->hasOneUse() && TI->getParent() == I->getParent() &&
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(isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) {
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unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
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unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
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unsigned OpReg = getRegForValue(TI->getOperand(0));
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(TstOpc))
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@ -1152,7 +1152,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
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CCMode = ARMCC::EQ;
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}
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unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
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unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
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.addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
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@ -1178,7 +1178,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
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// Regardless, the compare has been done in the predecessor block,
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// and it left a value for us in a virtual register. Ergo, we test
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// the one-bit value left in the virtual register.
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unsigned TstOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
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unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc))
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.addReg(CmpReg).addImm(1));
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@ -1188,7 +1188,7 @@ bool ARMFastISel::SelectBranch(const Instruction *I) {
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CCMode = ARMCC::EQ;
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}
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unsigned BrOpc = isThumb ? ARM::t2Bcc : ARM::Bcc;
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unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc))
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.addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
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FastEmitBranch(FBB, DL);
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@ -1223,7 +1223,7 @@ bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value,
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needsExt = true;
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// Intentional fall-through.
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case MVT::i32:
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CmpOpc = isThumb ? ARM::t2CMPrr : ARM::CMPrr;
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CmpOpc = isThumb2 ? ARM::t2CMPrr : ARM::CMPrr;
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break;
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}
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@ -1272,8 +1272,8 @@ bool ARMFastISel::SelectCmp(const Instruction *I) {
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// Now set a register based on the comparison. Explicitly set the predicates
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// here.
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unsigned MovCCOpc = isThumb ? ARM::t2MOVCCi : ARM::MOVCCi;
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TargetRegisterClass *RC = isThumb ? ARM::rGPRRegisterClass
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unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi;
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TargetRegisterClass *RC = isThumb2 ? ARM::rGPRRegisterClass
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: ARM::GPRRegisterClass;
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unsigned DestReg = createResultReg(RC);
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Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0);
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@ -1418,11 +1418,11 @@ bool ARMFastISel::SelectSelect(const Instruction *I) {
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unsigned Op2Reg = getRegForValue(I->getOperand(2));
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if (Op2Reg == 0) return false;
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unsigned CmpOpc = isThumb ? ARM::t2TSTri : ARM::TSTri;
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unsigned CmpOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc))
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.addReg(CondReg).addImm(1));
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unsigned ResultReg = createResultReg(RC);
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unsigned MovCCOpc = isThumb ? ARM::t2MOVCCr : ARM::MOVCCr;
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unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr;
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BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
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.addReg(Op1Reg).addReg(Op2Reg)
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.addImm(ARMCC::EQ).addReg(ARM::CPSR);
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@ -1788,7 +1788,7 @@ bool ARMFastISel::SelectRet(const Instruction *I) {
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MRI.addLiveOut(VA.getLocReg());
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}
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unsigned RetOpc = isThumb ? ARM::tBX_RET : ARM::BX_RET;
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unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET;
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AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(RetOpc)));
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return true;
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@ -1798,7 +1798,7 @@ unsigned ARMFastISel::ARMSelectCallOp(const GlobalValue *GV) {
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// Darwin needs the r9 versions of the opcodes.
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bool isDarwin = Subtarget->isTargetDarwin();
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if (isThumb) {
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if (isThumb2) {
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return isDarwin ? ARM::tBLr9 : ARM::tBL;
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} else {
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return isDarwin ? ARM::BLr9 : ARM::BL;
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@ -1864,7 +1864,7 @@ bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) {
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// TODO: Turn this into the table of arm call ops.
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MachineInstrBuilder MIB;
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unsigned CallOpc = ARMSelectCallOp(NULL);
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if(isThumb)
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if(isThumb2)
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// Explicitly adding the predicate here.
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MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(CallOpc)))
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@ -1979,7 +1979,7 @@ bool ARMFastISel::SelectCall(const Instruction *I) {
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MachineInstrBuilder MIB;
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unsigned CallOpc = ARMSelectCallOp(GV);
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// Explicitly adding the predicate here.
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if(isThumb)
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if(isThumb2)
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// Explicitly adding the predicate here.
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MIB = AddDefaultPred(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
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TII.get(CallOpc)))
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@ -2040,20 +2040,20 @@ unsigned ARMFastISel::ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT,
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case MVT::i16:
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if (!Subtarget->hasV6Ops()) return 0;
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if (isZExt)
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Opc = isThumb ? ARM::t2UXTH : ARM::UXTH;
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Opc = isThumb2 ? ARM::t2UXTH : ARM::UXTH;
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else
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Opc = isThumb ? ARM::t2SXTH : ARM::SXTH;
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Opc = isThumb2 ? ARM::t2SXTH : ARM::SXTH;
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break;
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case MVT::i8:
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if (!Subtarget->hasV6Ops()) return 0;
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if (isZExt)
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Opc = isThumb ? ARM::t2UXTB : ARM::UXTB;
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Opc = isThumb2 ? ARM::t2UXTB : ARM::UXTB;
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else
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Opc = isThumb ? ARM::t2SXTB : ARM::SXTB;
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Opc = isThumb2 ? ARM::t2SXTB : ARM::SXTB;
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break;
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case MVT::i1:
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if (isZExt) {
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Opc = isThumb ? ARM::t2ANDri : ARM::ANDri;
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Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri;
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isBoolZext = true;
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break;
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}
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