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- Added a few target hooks to generate load / store instructions from / to any

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address (not just from / to frameindexes).
- Added target hooks to unfold load / store instructions / SDNodes into separate
load, data processing, store instructions / SDNodes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42621 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng
2007-10-05 01:32:41 +00:00
parent 39305cf553
commit 66f0f64082
11 changed files with 505 additions and 85 deletions
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50
lib/Target/Alpha/AlphaRegisterInfo.cpp
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@@ -82,6 +82,31 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
abort();
}
void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const {
unsigned Opc = 0;
if (RC == Alpha::F4RCRegisterClass)
Opc = Alpha::STS;
else if (RC == Alpha::F8RCRegisterClass)
Opc = Alpha::STT;
else if (RC == Alpha::GPRCRegisterClass)
Opc = Alpha::STQ;
else
abort();
MachineInstrBuilder MIB =
BuildMI(TII.get(Opc)).addReg(SrcReg, false, false, true);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
else
MIB.addImm(MO.getImm());
}
NewMIs.push_back(MIB);
}
void
AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
@@ -102,6 +127,31 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
abort();
}
void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
SmallVector<MachineOperand,4> Addr,
const TargetRegisterClass *RC,
SmallVector<MachineInstr*, 4> &NewMIs) const {
unsigned Opc = 0;
if (RC == Alpha::F4RCRegisterClass)
Opc = Alpha::LDS;
else if (RC == Alpha::F8RCRegisterClass)
Opc = Alpha::LDT;
else if (RC == Alpha::GPRCRegisterClass)
Opc = Alpha::LDQ;
else
abort();
MachineInstrBuilder MIB =
BuildMI(TII.get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
MIB.addReg(MO.getReg(), MO.isDef(), MO.isImplicit());
else
MIB.addImm(MO.getImm());
}
NewMIs.push_back(MIB);
}
MachineInstr *AlphaRegisterInfo::foldMemoryOperand(MachineInstr *MI,
unsigned OpNum,
int FrameIndex) const {