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Vector fneg must be expanded into fsub -0.0, X.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40586 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2007-07-30 07:51:22 +00:00
parent db9530599e
commit 66ffe6be0c
3 changed files with 21 additions and 2 deletions
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11
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -259,6 +259,7 @@ PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
@ -523,6 +524,16 @@ bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
return true;
}
/// isAllNegativeZeroVector - Returns true if all elements of build_vector
/// are -0.0.
bool PPC::isAllNegativeZeroVector(SDNode *N) {
assert(N->getOpcode() == ISD::BUILD_VECTOR);
if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
return CFP->isExactlyValue(-0.0);
return false;
}
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {

4
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -160,6 +160,10 @@ namespace llvm {
/// VSPLTB/VSPLTH/VSPLTW.
bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
/// isAllNegativeZeroVector - Returns true if all elements of build_vector
/// are -0.0.
bool isAllNegativeZeroVector(SDNode *N);
/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);

8
lib/Target/PowerPC/PPCInstrAltivec.td
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@ -70,7 +70,6 @@ def VMRGHW_unary_shuffle_mask : PatLeaf<(build_vector), [{
return PPC::isVMRGHShuffleMask(N, 4, true);
}]>;
def VSLDOI_get_imm : SDNodeXForm<build_vector, [{
return getI32Imm(PPC::isVSLDOIShuffleMask(N, false));
}]>;
@ -133,6 +132,10 @@ def vecspltisw : PatLeaf<(build_vector), [{
return PPC::get_VSPLTI_elt(N, 4, *CurDAG).Val != 0;
}], VSPLTISW_get_imm>;
def V_immneg0 : PatLeaf<(build_vector), [{
return PPC::isAllNegativeZeroVector(N);
}]>;
//===----------------------------------------------------------------------===//
// Helpers for defining instructions that directly correspond to intrinsics.
@ -228,7 +231,8 @@ def VMADDFP : VAForm_1<46, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
Requires<[FPContractions]>;
def VNMSUBFP: VAForm_1<47, (outs VRRC:$vD), (ins VRRC:$vA, VRRC:$vC, VRRC:$vB),
"vnmsubfp $vD, $vA, $vC, $vB", VecFP,
[(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
[(set VRRC:$vD, (fsub V_immneg0,
(fsub (fmul VRRC:$vA, VRRC:$vC),
VRRC:$vB)))]>,
Requires<[FPContractions]>;