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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159035 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -55,11 +55,11 @@ struct X86AddressMode {
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: BaseType(RegBase), Scale(1), IndexReg(0), Disp(0), GV(0), GVOpFlags(0) {
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Base.Reg = 0;
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}
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void getFullAddress(SmallVectorImpl<MachineOperand> &MO) {
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assert(Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8);
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if (BaseType == X86AddressMode::RegBase)
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MO.push_back(MachineOperand::CreateReg(Base.Reg, false, false,
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false, false, false, 0, false));
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@ -67,16 +67,16 @@ struct X86AddressMode {
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assert(BaseType == X86AddressMode::FrameIndexBase);
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MO.push_back(MachineOperand::CreateFI(Base.FrameIndex));
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}
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MO.push_back(MachineOperand::CreateImm(Scale));
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MO.push_back(MachineOperand::CreateReg(IndexReg, false, false,
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false, false, false, 0, false));
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if (GV)
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MO.push_back(MachineOperand::CreateGA(GV, Disp, GVOpFlags));
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else
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MO.push_back(MachineOperand::CreateImm(Disp));
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MO.push_back(MachineOperand::CreateReg(0, false, false,
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false, false, false, 0, false));
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}
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@ -122,7 +122,7 @@ static inline const MachineInstrBuilder &
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addFullAddress(const MachineInstrBuilder &MIB,
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const X86AddressMode &AM) {
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assert(AM.Scale == 1 || AM.Scale == 2 || AM.Scale == 4 || AM.Scale == 8);
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if (AM.BaseType == X86AddressMode::RegBase)
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MIB.addReg(AM.Base.Reg);
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else {
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@ -135,7 +135,7 @@ addFullAddress(const MachineInstrBuilder &MIB,
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MIB.addGlobalAddress(AM.GV, AM.Disp, AM.GVOpFlags);
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else
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MIB.addImm(AM.Disp);
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return MIB.addReg(0);
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}
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