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Disable the load-shrinking optimization from looking at

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anything larger than 64-bits, avoiding a crash.  This should
really be fixed to use APInts, though type legalization happens
to help us out and we get good code on the attached testcase at
least.

This fixes rdar://6836460


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70360 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-04-29 03:45:07 +00:00
parent f0aa4850ce
commit 672452d5a0
2 changed files with 22 additions and 3 deletions
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7
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1538,15 +1538,18 @@ TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
N0.getOperand(0).getNode()->hasOneUse() &&
isa<ConstantSDNode>(N0.getOperand(1))) {
LoadSDNode *Lod = cast<LoadSDNode>(N0.getOperand(0));
uint64_t Mask = cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
uint64_t bestMask = 0;
unsigned bestWidth = 0, bestOffset = 0;
if (!Lod->isVolatile() && Lod->isUnindexed()) {
if (!Lod->isVolatile() && Lod->isUnindexed() &&
// FIXME: This uses getZExtValue() below so it only works on i64 and
// below.
N0.getValueType().getSizeInBits() <= 64) {
unsigned origWidth = N0.getValueType().getSizeInBits();
// We can narrow (e.g.) 16-bit extending loads on 32-bit target to
// 8 bits, but have to be careful...
if (Lod->getExtensionType() != ISD::NON_EXTLOAD)
origWidth = Lod->getMemoryVT().getSizeInBits();
uint64_t Mask =cast<ConstantSDNode>(N0.getOperand(1))->getZExtValue();
for (unsigned width = origWidth / 2; width>=8; width /= 2) {
uint64_t newMask = (1ULL << width) - 1;
for (unsigned offset=0; offset<origWidth/width; offset++) {

16
test/CodeGen/Generic/2009-04-28-i128-cmp-crash.ll Normal file
View File

@ -0,0 +1,16 @@
; RUN: llvm-as < %s | llc
; rdar://6836460
define i32 @test(i128* %P) nounwind {
entry:
%tmp48 = load i128* %P
%and49 = and i128 %tmp48, 18446744073709551616 ; <i128> [#uses=1]
%tobool = icmp ne i128 %and49, 0 ; <i1> [#uses=1]
br i1 %tobool, label %if.then50, label %if.end61
if.then50: ; preds = %if.then20
ret i32 1241
if.end61: ; preds = %if.then50, %if.then20, %entry
ret i32 123
}