6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-04 05:17:07 +00:00
Code Issues Projects Releases Wiki Activity

Added phi elimination code

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1265 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Ruchira Sasanka
2001-11-12 14:45:33 +00:00
parent b2490fc4fb
commit 67a463ac04
3 changed files with 55 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
lib/Target/SparcV9/SparcV9InstrSelection.cpp
View File

@@ -943,11 +943,12 @@ ForwardOperand(InstructionNode* treeNode,
} }
void
void UltraSparcInstrInfo::
CreateCopyInstructionsByType(const TargetMachine& target, CreateCopyInstructionsByType(const TargetMachine& target,
Value* src, Value* src,
Instruction* dest, Instruction* dest,
vector<MachineInstr*>& minstrVec) vector<MachineInstr*>& minstrVec) const
{ {
bool loadConstantToReg = false; bool loadConstantToReg = false;
@@ -1004,6 +1005,7 @@ CreateCopyInstructionsByType(const TargetMachine& target,
} }
//******************* Externally Visible Functions *************************/ //******************* Externally Visible Functions *************************/
@@ -2048,7 +2050,7 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
else else
{ {
vector<MachineInstr*> minstrVec; vector<MachineInstr*> minstrVec;
CreateCopyInstructionsByType(target, target.getInstrInfo().CreateCopyInstructionsByType(target,
subtreeRoot->getInstruction()->getOperand(forwardOperandNum), subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
subtreeRoot->getInstruction(), minstrVec); subtreeRoot->getInstruction(), minstrVec);
assert(minstrVec.size() > 0); assert(minstrVec.size() > 0);

9
lib/Target/SparcV9/SparcV9Internals.h
View File

@@ -139,6 +139,15 @@ public:
vector<MachineInstr*>& minstrVec, vector<MachineInstr*>& minstrVec,
vector<TmpInstruction*>& tempVec, vector<TmpInstruction*>& tempVec,
TargetMachine& target) const; TargetMachine& target) const;
// create copy instruction(s)
virtual void
CreateCopyInstructionsByType(const TargetMachine& target,
Value* src,
Instruction* dest,
vector<MachineInstr*>& minstrVec) const;
}; };

37
lib/Target/SparcV9/SparcV9RegInfo.cpp
View File

@@ -893,7 +893,6 @@ void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
// register number // register number
//--------------------------------------------------------------------------- //---------------------------------------------------------------------------
MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg, MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
const unsigned DestReg, const unsigned DestReg,
const int RegType) const { const int RegType) const {
@@ -1040,24 +1039,56 @@ MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
// Following method is Not needed now
//---------------------------------------------------------------------------
// Generate a copy instruction to copy a value to another. Temporarily
// used by PhiElimination code.
//---------------------------------------------------------------------------
MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{ MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{
int RegType = getRegType( Src );
assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
MachineInstr * MI = NULL; MachineInstr * MI = NULL;
switch( RegType ) {
case IntRegType:
MI = new MachineInstr(ADD, 3); MI = new MachineInstr(ADD, 3);
MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false); MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
MI->SetMachineOperand(1, SparcIntRegOrder::g0, false); MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true); MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true);
break;
case FPSingleRegType:
MI = new MachineInstr(FMOVS, 2);
MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
break;
case FPDoubleRegType:
MI = new MachineInstr(FMOVD, 2);
MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
break;
default:
assert(0 && "Unknow RegType in CpValu2Value");
}
return MI; return MI;
} }
//---------------------------------------------------------------------------- //----------------------------------------------------------------------------
// This method inserts caller saving/restoring instructons before/after // This method inserts caller saving/restoring instructons before/after
// a call machine instruction. // a call machine instruction.