diff --git a/test/CodeGen/ARM/vneg.ll b/test/CodeGen/ARM/vneg.ll index e5dc832a764..e560bdd2aa8 100644 --- a/test/CodeGen/ARM/vneg.ll +++ b/test/CodeGen/ARM/vneg.ll @@ -1,52 +1,64 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vneg\\.s8} %t | count 2 -; RUN: grep {vneg\\.s16} %t | count 2 -; RUN: grep {vneg\\.s32} %t | count 2 -; RUN: grep {vneg\\.f32} %t | count 2 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind { +;CHECK: vnegs8: +;CHECK: vneg.s8 %tmp1 = load <8 x i8>* %A %tmp2 = sub <8 x i8> zeroinitializer, %tmp1 ret <8 x i8> %tmp2 } define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind { +;CHECK: vnegs16: +;CHECK: vneg.s16 %tmp1 = load <4 x i16>* %A %tmp2 = sub <4 x i16> zeroinitializer, %tmp1 ret <4 x i16> %tmp2 } define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind { +;CHECK: vnegs32: +;CHECK: vneg.s32 %tmp1 = load <2 x i32>* %A %tmp2 = sub <2 x i32> zeroinitializer, %tmp1 ret <2 x i32> %tmp2 } define <2 x float> @vnegf32(<2 x float>* %A) nounwind { +;CHECK: vnegf32: +;CHECK: vneg.f32 %tmp1 = load <2 x float>* %A %tmp2 = sub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1 ret <2 x float> %tmp2 } define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind { +;CHECK: vnegQs8: +;CHECK: vneg.s8 %tmp1 = load <16 x i8>* %A %tmp2 = sub <16 x i8> zeroinitializer, %tmp1 ret <16 x i8> %tmp2 } define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind { +;CHECK: vnegQs16: +;CHECK: vneg.s16 %tmp1 = load <8 x i16>* %A %tmp2 = sub <8 x i16> zeroinitializer, %tmp1 ret <8 x i16> %tmp2 } define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind { +;CHECK: vnegQs32: +;CHECK: vneg.s32 %tmp1 = load <4 x i32>* %A %tmp2 = sub <4 x i32> zeroinitializer, %tmp1 ret <4 x i32> %tmp2 } define <4 x float> @vnegQf32(<4 x float>* %A) nounwind { +;CHECK: vnegQf32: +;CHECK: vneg.f32 %tmp1 = load <4 x float>* %A %tmp2 = sub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1 ret <4 x float> %tmp2 diff --git a/test/CodeGen/ARM/vorn.ll b/test/CodeGen/ARM/vorn.ll index 23cbbf0592c..bef6d37e669 100644 --- a/test/CodeGen/ARM/vorn.ll +++ b/test/CodeGen/ARM/vorn.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep vorn %t | count 8 -; Note: function names do not include "vorn" to allow simple grep for opcodes +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: v_orni8: +;CHECK: vorn %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = xor <8 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > @@ -11,6 +11,8 @@ define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: v_orni16: +;CHECK: vorn %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = xor <4 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1 > @@ -19,6 +21,8 @@ define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: v_orni32: +;CHECK: vorn %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = xor <2 x i32> %tmp2, < i32 -1, i32 -1 > @@ -27,6 +31,8 @@ define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind { +;CHECK: v_orni64: +;CHECK: vorn %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B %tmp3 = xor <1 x i64> %tmp2, < i64 -1 > @@ -35,6 +41,8 @@ define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { +;CHECK: v_ornQi8: +;CHECK: vorn %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = xor <16 x i8> %tmp2, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 > @@ -43,6 +51,8 @@ define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { +;CHECK: v_ornQi16: +;CHECK: vorn %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B %tmp3 = xor <8 x i16> %tmp2, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 > @@ -51,6 +61,8 @@ define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { +;CHECK: v_ornQi32: +;CHECK: vorn %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B %tmp3 = xor <4 x i32> %tmp2, < i32 -1, i32 -1, i32 -1, i32 -1 > @@ -59,6 +71,8 @@ define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { +;CHECK: v_ornQi64: +;CHECK: vorn %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B %tmp3 = xor <2 x i64> %tmp2, < i64 -1, i64 -1 > diff --git a/test/CodeGen/ARM/vorr.ll b/test/CodeGen/ARM/vorr.ll index 5788bb2cb68..e9777ab7649 100644 --- a/test/CodeGen/ARM/vorr.ll +++ b/test/CodeGen/ARM/vorr.ll @@ -1,8 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep vorr %t | count 8 -; Note: function names do not include "vorr" to allow simple grep for opcodes +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: v_orri8: +;CHECK: vorr %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = or <8 x i8> %tmp1, %tmp2 @@ -10,6 +10,8 @@ define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: v_orri16: +;CHECK: vorr %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = or <4 x i16> %tmp1, %tmp2 @@ -17,6 +19,8 @@ define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: v_orri32: +;CHECK: vorr %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = or <2 x i32> %tmp1, %tmp2 @@ -24,6 +28,8 @@ define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { +;CHECK: v_orri64: +;CHECK: vorr %tmp1 = load <1 x i64>* %A %tmp2 = load <1 x i64>* %B %tmp3 = or <1 x i64> %tmp1, %tmp2 @@ -31,6 +37,8 @@ define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind { } define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { +;CHECK: v_orrQi8: +;CHECK: vorr %tmp1 = load <16 x i8>* %A %tmp2 = load <16 x i8>* %B %tmp3 = or <16 x i8> %tmp1, %tmp2 @@ -38,6 +46,8 @@ define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind { } define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { +;CHECK: v_orrQi16: +;CHECK: vorr %tmp1 = load <8 x i16>* %A %tmp2 = load <8 x i16>* %B %tmp3 = or <8 x i16> %tmp1, %tmp2 @@ -45,6 +55,8 @@ define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind { } define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { +;CHECK: v_orrQi32: +;CHECK: vorr %tmp1 = load <4 x i32>* %A %tmp2 = load <4 x i32>* %B %tmp3 = or <4 x i32> %tmp1, %tmp2 @@ -52,6 +64,8 @@ define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind { } define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind { +;CHECK: v_orrQi64: +;CHECK: vorr %tmp1 = load <2 x i64>* %A %tmp2 = load <2 x i64>* %B %tmp3 = or <2 x i64> %tmp1, %tmp2 diff --git a/test/CodeGen/ARM/vpadal.ll b/test/CodeGen/ARM/vpadal.ll index 8423b1b2c48..7296e936cd7 100644 --- a/test/CodeGen/ARM/vpadal.ll +++ b/test/CodeGen/ARM/vpadal.ll @@ -1,12 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vpadal\\.s8} %t | count 2 -; RUN: grep {vpadal\\.s16} %t | count 2 -; RUN: grep {vpadal\\.s32} %t | count 2 -; RUN: grep {vpadal\\.u8} %t | count 2 -; RUN: grep {vpadal\\.u16} %t | count 2 -; RUN: grep {vpadal\\.u32} %t | count 2 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind { +;CHECK: vpadals8: +;CHECK: vpadal.s8 %tmp1 = load <4 x i16>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpadals.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2) @@ -14,6 +10,8 @@ define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind { } define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind { +;CHECK: vpadals16: +;CHECK: vpadal.s16 %tmp1 = load <2 x i32>* %A %tmp2 = load <4 x i16>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpadals.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2) @@ -21,6 +19,8 @@ define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind { } define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind { +;CHECK: vpadals32: +;CHECK: vpadal.s32 %tmp1 = load <1 x i64>* %A %tmp2 = load <2 x i32>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vpadals.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2) @@ -28,6 +28,8 @@ define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind { } define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind { +;CHECK: vpadalu8: +;CHECK: vpadal.u8 %tmp1 = load <4 x i16>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpadalu.v4i16.v8i8(<4 x i16> %tmp1, <8 x i8> %tmp2) @@ -35,6 +37,8 @@ define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind { } define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind { +;CHECK: vpadalu16: +;CHECK: vpadal.u16 %tmp1 = load <2 x i32>* %A %tmp2 = load <4 x i16>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpadalu.v2i32.v4i16(<2 x i32> %tmp1, <4 x i16> %tmp2) @@ -42,6 +46,8 @@ define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind { } define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind { +;CHECK: vpadalu32: +;CHECK: vpadal.u32 %tmp1 = load <1 x i64>* %A %tmp2 = load <2 x i32>* %B %tmp3 = call <1 x i64> @llvm.arm.neon.vpadalu.v1i64.v2i32(<1 x i64> %tmp1, <2 x i32> %tmp2) @@ -49,6 +55,8 @@ define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind { } define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind { +;CHECK: vpadalQs8: +;CHECK: vpadal.s8 %tmp1 = load <8 x i16>* %A %tmp2 = load <16 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vpadals.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2) @@ -56,6 +64,8 @@ define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind { } define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind { +;CHECK: vpadalQs16: +;CHECK: vpadal.s16 %tmp1 = load <4 x i32>* %A %tmp2 = load <8 x i16>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vpadals.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2) @@ -63,6 +73,8 @@ define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind { } define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind { +;CHECK: vpadalQs32: +;CHECK: vpadal.s32 %tmp1 = load <2 x i64>* %A %tmp2 = load <4 x i32>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vpadals.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2) @@ -70,6 +82,8 @@ define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind { } define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind { +;CHECK: vpadalQu8: +;CHECK: vpadal.u8 %tmp1 = load <8 x i16>* %A %tmp2 = load <16 x i8>* %B %tmp3 = call <8 x i16> @llvm.arm.neon.vpadalu.v8i16.v16i8(<8 x i16> %tmp1, <16 x i8> %tmp2) @@ -77,6 +91,8 @@ define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind { } define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind { +;CHECK: vpadalQu16: +;CHECK: vpadal.u16 %tmp1 = load <4 x i32>* %A %tmp2 = load <8 x i16>* %B %tmp3 = call <4 x i32> @llvm.arm.neon.vpadalu.v4i32.v8i16(<4 x i32> %tmp1, <8 x i16> %tmp2) @@ -84,6 +100,8 @@ define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind { } define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind { +;CHECK: vpadalQu32: +;CHECK: vpadal.u32 %tmp1 = load <2 x i64>* %A %tmp2 = load <4 x i32>* %B %tmp3 = call <2 x i64> @llvm.arm.neon.vpadalu.v2i64.v4i32(<2 x i64> %tmp1, <4 x i32> %tmp2) diff --git a/test/CodeGen/ARM/vpadd.ll b/test/CodeGen/ARM/vpadd.ll index 3e6179d6bc0..69cfb233657 100644 --- a/test/CodeGen/ARM/vpadd.ll +++ b/test/CodeGen/ARM/vpadd.ll @@ -1,10 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vpadd\\.i8} %t | count 1 -; RUN: grep {vpadd\\.i16} %t | count 1 -; RUN: grep {vpadd\\.i32} %t | count 1 -; RUN: grep {vpadd\\.f32} %t | count 1 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vpaddi8: +;CHECK: vpadd.i8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -12,6 +10,8 @@ define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vpaddi16: +;CHECK: vpadd.i16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -19,6 +19,8 @@ define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vpaddi32: +;CHECK: vpadd.i32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -26,6 +28,8 @@ define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind { +;CHECK: vpaddf32: +;CHECK: vpadd.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) diff --git a/test/CodeGen/ARM/vpaddl.ll b/test/CodeGen/ARM/vpaddl.ll index d975710e40e..44c4e30f1ec 100644 --- a/test/CodeGen/ARM/vpaddl.ll +++ b/test/CodeGen/ARM/vpaddl.ll @@ -1,78 +1,96 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vpaddl\\.s8} %t | count 2 -; RUN: grep {vpaddl\\.s16} %t | count 2 -; RUN: grep {vpaddl\\.s32} %t | count 2 -; RUN: grep {vpaddl\\.u8} %t | count 2 -; RUN: grep {vpaddl\\.u16} %t | count 2 -; RUN: grep {vpaddl\\.u32} %t | count 2 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind { +;CHECK: vpaddls8: +;CHECK: vpaddl.s8 %tmp1 = load <8 x i8>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1) ret <4 x i16> %tmp2 } define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind { +;CHECK: vpaddls16: +;CHECK: vpaddl.s16 %tmp1 = load <4 x i16>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1) ret <2 x i32> %tmp2 } define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind { +;CHECK: vpaddls32: +;CHECK: vpaddl.s32 %tmp1 = load <2 x i32>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1) ret <1 x i64> %tmp2 } define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind { +;CHECK: vpaddlu8: +;CHECK: vpaddl.u8 %tmp1 = load <8 x i8>* %A %tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1) ret <4 x i16> %tmp2 } define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind { +;CHECK: vpaddlu16: +;CHECK: vpaddl.u16 %tmp1 = load <4 x i16>* %A %tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1) ret <2 x i32> %tmp2 } define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind { +;CHECK: vpaddlu32: +;CHECK: vpaddl.u32 %tmp1 = load <2 x i32>* %A %tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1) ret <1 x i64> %tmp2 } define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind { +;CHECK: vpaddlQs8: +;CHECK: vpaddl.s8 %tmp1 = load <16 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1) ret <8 x i16> %tmp2 } define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind { +;CHECK: vpaddlQs16: +;CHECK: vpaddl.s16 %tmp1 = load <8 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1) ret <4 x i32> %tmp2 } define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind { +;CHECK: vpaddlQs32: +;CHECK: vpaddl.s32 %tmp1 = load <4 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1) ret <2 x i64> %tmp2 } define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind { +;CHECK: vpaddlQu8: +;CHECK: vpaddl.u8 %tmp1 = load <16 x i8>* %A %tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1) ret <8 x i16> %tmp2 } define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind { +;CHECK: vpaddlQu16: +;CHECK: vpaddl.u16 %tmp1 = load <8 x i16>* %A %tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1) ret <4 x i32> %tmp2 } define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind { +;CHECK: vpaddlQu32: +;CHECK: vpaddl.u32 %tmp1 = load <4 x i32>* %A %tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1) ret <2 x i64> %tmp2 diff --git a/test/CodeGen/ARM/vpmax.ll b/test/CodeGen/ARM/vpmax.ll index 8f6fb57215a..b2a4a6e760a 100644 --- a/test/CodeGen/ARM/vpmax.ll +++ b/test/CodeGen/ARM/vpmax.ll @@ -1,13 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vpmax\\.s8} %t | count 1 -; RUN: grep {vpmax\\.s16} %t | count 1 -; RUN: grep {vpmax\\.s32} %t | count 1 -; RUN: grep {vpmax\\.u8} %t | count 1 -; RUN: grep {vpmax\\.u16} %t | count 1 -; RUN: grep {vpmax\\.u32} %t | count 1 -; RUN: grep {vpmax\\.f32} %t | count 1 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vpmaxs8: +;CHECK: vpmax.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxs.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -15,6 +10,8 @@ define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vpmaxs16: +;CHECK: vpmax.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxs.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -22,6 +19,8 @@ define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vpmaxs32: +;CHECK: vpmax.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxs.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -29,6 +28,8 @@ define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vpmaxu8: +;CHECK: vpmax.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpmaxu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -36,6 +37,8 @@ define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vpmaxu16: +;CHECK: vpmax.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpmaxu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -43,6 +46,8 @@ define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vpmaxu32: +;CHECK: vpmax.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpmaxu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -50,6 +55,8 @@ define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind { +;CHECK: vpmaxf32: +;CHECK: vpmax.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vpmaxs.v2f32(<2 x float> %tmp1, <2 x float> %tmp2) diff --git a/test/CodeGen/ARM/vpmin.ll b/test/CodeGen/ARM/vpmin.ll index 3771258839a..d27043f6179 100644 --- a/test/CodeGen/ARM/vpmin.ll +++ b/test/CodeGen/ARM/vpmin.ll @@ -1,13 +1,8 @@ -; RUN: llc < %s -march=arm -mattr=+neon > %t -; RUN: grep {vpmin\\.s8} %t | count 1 -; RUN: grep {vpmin\\.s16} %t | count 1 -; RUN: grep {vpmin\\.s32} %t | count 1 -; RUN: grep {vpmin\\.u8} %t | count 1 -; RUN: grep {vpmin\\.u16} %t | count 1 -; RUN: grep {vpmin\\.u32} %t | count 1 -; RUN: grep {vpmin\\.f32} %t | count 1 +; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vpmins8: +;CHECK: vpmin.s8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpmins.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -15,6 +10,8 @@ define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vpmins16: +;CHECK: vpmin.s16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpmins.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -22,6 +19,8 @@ define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vpmins32: +;CHECK: vpmin.s32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpmins.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -29,6 +28,8 @@ define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { +;CHECK: vpminu8: +;CHECK: vpmin.u8 %tmp1 = load <8 x i8>* %A %tmp2 = load <8 x i8>* %B %tmp3 = call <8 x i8> @llvm.arm.neon.vpminu.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2) @@ -36,6 +37,8 @@ define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind { } define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { +;CHECK: vpminu16: +;CHECK: vpmin.u16 %tmp1 = load <4 x i16>* %A %tmp2 = load <4 x i16>* %B %tmp3 = call <4 x i16> @llvm.arm.neon.vpminu.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2) @@ -43,6 +46,8 @@ define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind { } define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { +;CHECK: vpminu32: +;CHECK: vpmin.u32 %tmp1 = load <2 x i32>* %A %tmp2 = load <2 x i32>* %B %tmp3 = call <2 x i32> @llvm.arm.neon.vpminu.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2) @@ -50,6 +55,8 @@ define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind { } define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind { +;CHECK: vpminf32: +;CHECK: vpmin.f32 %tmp1 = load <2 x float>* %A %tmp2 = load <2 x float>* %B %tmp3 = call <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float> %tmp1, <2 x float> %tmp2)