mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Add MC encodings for VCVT* instrunctions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116431 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
@@ -317,12 +317,15 @@ def VCMPES : ASuI_Encode<0b11101, 0b11, 0b0100, 0b11, 0,
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IIC_fpCMP32, "vcmpe", ".f32\t$Sd, $Sm",
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[(arm_cmpfp SPR:$Sd, SPR:$Sm)]>;
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def VCMPD : ADuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins DPR:$a, DPR:$b),
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IIC_fpCMP64, "vcmp", ".f64\t$a, $b",
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// FIXME: Verify encoding after integrated assembler is working.
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def VCMPD : ADuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
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(outs), (ins DPR:$Dd, DPR:$Dm),
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IIC_fpCMP64, "vcmp", ".f64\t$Dd, $Dm",
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[/* For disassembly only; pattern left blank */]>;
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def VCMPS : ASuI<0b11101, 0b11, 0b0100, 0b01, 0, (outs), (ins SPR:$a, SPR:$b),
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IIC_fpCMP32, "vcmp", ".f32\t$a, $b",
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def VCMPS : ASuI_Encode<0b11101, 0b11, 0b0100, 0b01, 0,
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(outs), (ins SPR:$Sd, SPR:$Sm),
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IIC_fpCMP32, "vcmp", ".f32\t$Sd, $Sm",
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[/* For disassembly only; pattern left blank */]>;
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}
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@@ -357,13 +360,22 @@ def VCMPEZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b11, 0,
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let Inst{5} = 0;
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}
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def VCMPZD : ADuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins DPR:$a),
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IIC_fpCMP64, "vcmp", ".f64\t$a, #0",
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[/* For disassembly only; pattern left blank */]>;
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// FIXME: Verify encoding after integrated assembler is working.
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def VCMPZD : ADuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
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(outs), (ins DPR:$Dd),
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IIC_fpCMP64, "vcmp", ".f64\t$Dd, #0",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{3-0} = 0b0000;
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let Inst{5} = 0;
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}
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def VCMPZS : ASuI<0b11101, 0b11, 0b0101, 0b01, 0, (outs), (ins SPR:$a),
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IIC_fpCMP32, "vcmp", ".f32\t$a, #0",
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[/* For disassembly only; pattern left blank */]>;
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def VCMPZS : ASuI_Encode<0b11101, 0b11, 0b0101, 0b01, 0,
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(outs), (ins SPR:$Sd),
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IIC_fpCMP32, "vcmp", ".f32\t$Sd, #0",
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[/* For disassembly only; pattern left blank */]> {
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let Inst{3-0} = 0b0000;
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let Inst{5} = 0;
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}
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}
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def VCVTDS : ASuI<0b11101, 0b11, 0b0111, 0b11, 0,
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@@ -404,6 +416,7 @@ def VCVTSD : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
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// Between half-precision and single-precision. For disassembly only.
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// FIXME: Verify encoding after integrated assembler is working.
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def VCVTBSH: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$dst), (ins SPR:$a),
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/* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$dst, $a",
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[/* For disassembly only; pattern left blank */]>;
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@@ -426,16 +439,6 @@ def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$dst), (ins SPR:$a),
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/* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$dst, $a",
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[/* For disassembly only; pattern left blank */]>;
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let neverHasSideEffects = 1 in {
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def VMOVD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
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(outs DPR:$Dd), (ins DPR:$Dm),
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IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
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def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
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} // neverHasSideEffects
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def VNEGD : ADuI_Encode<0b11101, 0b11, 0b0001, 0b01, 0,
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(outs DPR:$Dd), (ins DPR:$Dm),
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IIC_fpUNA64, "vneg", ".f64\t$Dd, $Dm",
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@@ -456,6 +459,16 @@ def VSQRTS : ASuI_Encode<0b11101, 0b11, 0b0001, 0b11, 0,
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IIC_fpSQRT32, "vsqrt", ".f32\t$Sd, $Sm",
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[(set SPR:$Sd, (fsqrt SPR:$Sm))]>;
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let neverHasSideEffects = 1 in {
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def VMOVD : ADuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
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(outs DPR:$Dd), (ins DPR:$Dm),
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IIC_fpUNA64, "vmov", ".f64\t$Dd, $Dm", []>;
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def VMOVS : ASuI_Encode<0b11101, 0b11, 0b0000, 0b01, 0,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpUNA32, "vmov", ".f32\t$Sd, $Sm", []>;
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} // neverHasSideEffects
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//===----------------------------------------------------------------------===//
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// FP <-> GPR Copies. Int <-> FP Conversions.
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//
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@@ -506,101 +519,167 @@ def VMOVSRR : AVConv5I<0b11000100, 0b1010,
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// FMRDL: SPR -> GPR
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// FMRRS: SPR -> GPR
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// FMRX: SPR system reg -> GPR
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// FMSRR: GPR -> SPR
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// FMXR: GPR -> VFP system reg
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// Int to FP:
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// Int -> FP:
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def VSITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
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(outs DPR:$dst), (ins SPR:$a),
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IIC_fpCVTID, "vcvt", ".f64.s32\t$dst, $a",
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[(set DPR:$dst, (f64 (arm_sitof SPR:$a)))]> {
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class AVConv1IDs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
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bits<4> opcod4, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
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pattern> {
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// Instruction operands.
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bits<5> Dd;
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bits<5> Sm;
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// Encode instruction operands.
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let Inst{3-0} = Sm{4-1};
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let Inst{5} = Sm{0};
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let Inst{15-12} = Dd{3-0};
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let Inst{22} = Dd{4};
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}
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class AVConv1InSs_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
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bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
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string opc, string asm, list<dag> pattern>
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: AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
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pattern> {
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// Instruction operands.
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bits<5> Sd;
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bits<5> Sm;
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// Encode instruction operands.
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let Inst{3-0} = Sm{4-1};
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let Inst{5} = Sm{0};
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let Inst{15-12} = Sd{4-1};
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let Inst{22} = Sd{0};
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}
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def VSITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
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(outs DPR:$Dd), (ins SPR:$Sm),
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IIC_fpCVTID, "vcvt", ".f64.s32\t$Dd, $Sm",
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[(set DPR:$Dd, (f64 (arm_sitof SPR:$Sm)))]> {
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let Inst{7} = 1; // s32
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}
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def VSITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
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(outs SPR:$dst),(ins SPR:$a),
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IIC_fpCVTIS, "vcvt", ".f32.s32\t$dst, $a",
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[(set SPR:$dst, (arm_sitof SPR:$a))]> {
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def VSITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
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(outs SPR:$Sd),(ins SPR:$Sm),
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IIC_fpCVTIS, "vcvt", ".f32.s32\t$Sd, $Sm",
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[(set SPR:$Sd, (arm_sitof SPR:$Sm))]> {
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let Inst{7} = 1; // s32
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}
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def VUITOD : AVConv1I<0b11101, 0b11, 0b1000, 0b1011,
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(outs DPR:$dst), (ins SPR:$a),
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IIC_fpCVTID, "vcvt", ".f64.u32\t$dst, $a",
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[(set DPR:$dst, (f64 (arm_uitof SPR:$a)))]> {
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def VUITOD : AVConv1IDs_Encode<0b11101, 0b11, 0b1000, 0b1011,
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(outs DPR:$Dd), (ins SPR:$Sm),
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IIC_fpCVTID, "vcvt", ".f64.u32\t$Dd, $Sm",
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[(set DPR:$Dd, (f64 (arm_uitof SPR:$Sm)))]> {
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let Inst{7} = 0; // u32
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}
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def VUITOS : AVConv1In<0b11101, 0b11, 0b1000, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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IIC_fpCVTIS, "vcvt", ".f32.u32\t$dst, $a",
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[(set SPR:$dst, (arm_uitof SPR:$a))]> {
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def VUITOS : AVConv1InSs_Encode<0b11101, 0b11, 0b1000, 0b1010,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpCVTIS, "vcvt", ".f32.u32\t$Sd, $Sm",
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[(set SPR:$Sd, (arm_uitof SPR:$Sm))]> {
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let Inst{7} = 0; // u32
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}
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// FP to Int:
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// FP -> Int:
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class AVConv1IsD_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
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bits<4> opcod4, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
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pattern> {
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// Instruction operands.
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bits<5> Sd;
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bits<5> Dm;
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// Encode instruction operands.
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let Inst{3-0} = Dm{3-0};
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let Inst{5} = Dm{4};
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let Inst{15-12} = Sd{4-1};
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let Inst{22} = Sd{0};
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}
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class AVConv1InsS_Encode<bits<5> opcod1, bits<2> opcod2, bits<4> opcod3,
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bits<4> opcod4, dag oops, dag iops,
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InstrItinClass itin, string opc, string asm,
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list<dag> pattern>
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: AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
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pattern> {
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// Instruction operands.
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bits<5> Sd;
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bits<5> Sm;
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// Encode instruction operands.
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let Inst{3-0} = Sm{4-1};
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let Inst{5} = Sm{0};
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let Inst{15-12} = Sd{4-1};
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let Inst{22} = Sd{0};
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}
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// Always set Z bit in the instruction, i.e. "round towards zero" variants.
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def VTOSIZD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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IIC_fpCVTDI, "vcvt", ".s32.f64\t$dst, $a",
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[(set SPR:$dst, (arm_ftosi (f64 DPR:$a)))]> {
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def VTOSIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
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(outs SPR:$Sd), (ins DPR:$Dm),
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IIC_fpCVTDI, "vcvt", ".s32.f64\t$Sd, $Dm",
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[(set SPR:$Sd, (arm_ftosi (f64 DPR:$Dm)))]> {
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let Inst{7} = 1; // Z bit
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}
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def VTOSIZS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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IIC_fpCVTSI, "vcvt", ".s32.f32\t$dst, $a",
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[(set SPR:$dst, (arm_ftosi SPR:$a))]> {
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def VTOSIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpCVTSI, "vcvt", ".s32.f32\t$Sd, $Sm",
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[(set SPR:$Sd, (arm_ftosi SPR:$Sm))]> {
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let Inst{7} = 1; // Z bit
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}
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def VTOUIZD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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IIC_fpCVTDI, "vcvt", ".u32.f64\t$dst, $a",
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[(set SPR:$dst, (arm_ftoui (f64 DPR:$a)))]> {
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def VTOUIZD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
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(outs SPR:$Sd), (ins DPR:$Dm),
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IIC_fpCVTDI, "vcvt", ".u32.f64\t$Sd, $Dm",
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[(set SPR:$Sd, (arm_ftoui (f64 DPR:$Dm)))]> {
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let Inst{7} = 1; // Z bit
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}
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def VTOUIZS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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IIC_fpCVTSI, "vcvt", ".u32.f32\t$dst, $a",
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[(set SPR:$dst, (arm_ftoui SPR:$a))]> {
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def VTOUIZS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpCVTSI, "vcvt", ".u32.f32\t$Sd, $Sm",
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[(set SPR:$Sd, (arm_ftoui SPR:$Sm))]> {
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let Inst{7} = 1; // Z bit
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}
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// And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
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// For disassembly only.
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let Uses = [FPSCR] in {
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def VTOSIRD : AVConv1I<0b11101, 0b11, 0b1101, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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IIC_fpCVTDI, "vcvtr", ".s32.f64\t$dst, $a",
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[(set SPR:$dst, (int_arm_vcvtr (f64 DPR:$a)))]> {
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// FIXME: Verify encoding after integrated assembler is working.
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def VTOSIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1101, 0b1011,
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(outs SPR:$Sd), (ins DPR:$Dm),
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IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
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[(set SPR:$Sd, (int_arm_vcvtr (f64 DPR:$Dm)))]>{
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let Inst{7} = 0; // Z bit
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}
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def VTOSIRS : AVConv1In<0b11101, 0b11, 0b1101, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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IIC_fpCVTSI, "vcvtr", ".s32.f32\t$dst, $a",
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[(set SPR:$dst, (int_arm_vcvtr SPR:$a))]> {
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def VTOSIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1101, 0b1010,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
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[(set SPR:$Sd, (int_arm_vcvtr SPR:$Sm))]> {
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let Inst{7} = 0; // Z bit
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}
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def VTOUIRD : AVConv1I<0b11101, 0b11, 0b1100, 0b1011,
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(outs SPR:$dst), (ins DPR:$a),
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IIC_fpCVTDI, "vcvtr", ".u32.f64\t$dst, $a",
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[(set SPR:$dst, (int_arm_vcvtru (f64 DPR:$a)))]> {
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def VTOUIRD : AVConv1IsD_Encode<0b11101, 0b11, 0b1100, 0b1011,
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(outs SPR:$Sd), (ins DPR:$Dm),
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IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
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[(set SPR:$Sd, (int_arm_vcvtru (f64 DPR:$Dm)))]> {
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let Inst{7} = 0; // Z bit
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}
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def VTOUIRS : AVConv1In<0b11101, 0b11, 0b1100, 0b1010,
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(outs SPR:$dst), (ins SPR:$a),
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IIC_fpCVTSI, "vcvtr", ".u32.f32\t$dst, $a",
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[(set SPR:$dst, (int_arm_vcvtru SPR:$a))]> {
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def VTOUIRS : AVConv1InsS_Encode<0b11101, 0b11, 0b1100, 0b1010,
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(outs SPR:$Sd), (ins SPR:$Sm),
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IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
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[(set SPR:$Sd, (int_arm_vcvtru SPR:$Sm))]> {
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let Inst{7} = 0; // Z bit
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}
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}
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@@ -192,3 +192,67 @@ entry:
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}
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declare float @sqrtf(float) readnone
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define double @f23(i32 %a) nounwind readnone {
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entry:
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; CHECK: f23
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; CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee]
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%conv = sitofp i32 %a to double
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ret double %conv
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}
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define float @f24(i32 %a) nounwind readnone {
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entry:
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; CHECK: f24
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; CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee]
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%conv = sitofp i32 %a to float
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ret float %conv
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}
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define double @f25(i32 %a) nounwind readnone {
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entry:
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; CHECK: f25
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; CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee]
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%conv = uitofp i32 %a to double
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ret double %conv
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||||
}
|
||||
|
||||
define float @f26(i32 %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f26
|
||||
; CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee]
|
||||
%conv = uitofp i32 %a to float
|
||||
ret float %conv
|
||||
}
|
||||
|
||||
define i32 @f27(double %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f27
|
||||
; CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee]
|
||||
%conv = fptosi double %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
define i32 @f28(float %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f28
|
||||
; CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee]
|
||||
%conv = fptosi float %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
define i32 @f29(double %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f29
|
||||
; CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee]
|
||||
%conv = fptoui double %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
define i32 @f30(float %a) nounwind readnone {
|
||||
entry:
|
||||
; CHECK: f30
|
||||
; CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee]
|
||||
%conv = fptoui float %a to i32
|
||||
ret i32 %conv
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user