6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-11-02 07:17:36 +00:00
Code Issues Projects Releases Wiki Activity

[mips] Implement shorthand add / sub forms for MIPS.

Browse Source 
Summary:
- If only two registers are passed to a three-register operation, then the
  first argument is both source and destination register.

- If a non-register is passed as the last argument, generate the immediate
  version of the instruction.

Also mark DADD commutative and add scheduling information (to the generic
scheduler), and implement DSUB.

Patch by David Chisnall
His work was sponsored by: DARPA, AFRL

CC: theraven

Differential Revision: http://llvm-reviews.chandlerc.com/D3148

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204605 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Daniel Sanders
2014-03-24 14:05:39 +00:00
parent b8cb709858
commit 67db74e02c
5 changed files with 138 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
lib/Target/Mips/AsmParser/MipsAsmParser.cpp
View File

@@ -16,6 +16,7 @@
#include "llvm/MC/MCContext.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCInstBuilder.h"
#include "llvm/MC/MCParser/MCAsmLexer.h"
#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
#include "llvm/MC/MCStreamer.h"
@@ -589,6 +590,7 @@ static const MCInstrDesc &getInstDesc(unsigned Opcode) {
bool MipsAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
SmallVectorImpl<MCInst> &Instructions) {
const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
Inst.setLoc(IDLoc);
if (MCID.isBranch() || MCID.isCall()) {
@@ -690,6 +692,10 @@ bool MipsAsmParser::needsExpansion(MCInst &Inst) {
case Mips::LoadImm32Reg:
case Mips::LoadAddr32Imm:
case Mips::LoadAddr32Reg:
case Mips::SUBi:
case Mips::SUBiu:
case Mips::DSUBi:
case Mips::DSUBiu:
return true;
default:
return false;
@@ -705,6 +711,30 @@ void MipsAsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
return expandLoadAddressImm(Inst, IDLoc, Instructions);
case Mips::LoadAddr32Reg:
return expandLoadAddressReg(Inst, IDLoc, Instructions);
case Mips::SUBi:
Instructions.push_back(MCInstBuilder(Mips::ADDi)
.addReg(Inst.getOperand(0).getReg())
.addReg(Inst.getOperand(1).getReg())
.addImm(-Inst.getOperand(2).getImm()));
return;
case Mips::SUBiu:
Instructions.push_back(MCInstBuilder(Mips::ADDiu)
.addReg(Inst.getOperand(0).getReg())
.addReg(Inst.getOperand(1).getReg())
.addImm(-Inst.getOperand(2).getImm()));
return;
case Mips::DSUBi:
Instructions.push_back(MCInstBuilder(Mips::DADDi)
.addReg(Inst.getOperand(0).getReg())
.addReg(Inst.getOperand(1).getReg())
.addImm(-Inst.getOperand(2).getImm()));
return;
case Mips::DSUBiu:
Instructions.push_back(MCInstBuilder(Mips::DADDiu)
.addReg(Inst.getOperand(0).getReg())
.addReg(Inst.getOperand(1).getReg())
.addImm(-Inst.getOperand(2).getImm()));
return;
}
}