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Fix PR18162 - Incorrect assertion assumed that the SDValue resno is zero.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196858 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nadav Rotem
2013-12-10 01:13:59 +00:00
parent d5cf7abce6
commit 6806e11612
2 changed files with 28 additions and 1 deletions
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2
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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@@ -9859,7 +9859,7 @@ SDValue DAGCombiner::visitCONCAT_VECTORS(SDNode *N) {
if (N->getNumOperands() == 2 && if (N->getNumOperands() == 2 &&
N->getOperand(1)->getOpcode() == ISD::UNDEF) { N->getOperand(1)->getOpcode() == ISD::UNDEF) {
SDValue In = N->getOperand(0); SDValue In = N->getOperand(0);
assert(In->getValueType(0).isVector() && "Must concat vectors"); assert(In.getValueType().isVector() && "Must concat vectors");
// Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr). // Transform: concat_vectors(scalar, undef) -> scalar_to_vector(sclr).
if (In->getOpcode() == ISD::BITCAST && if (In->getOpcode() == ISD::BITCAST &&

27
test/CodeGen/X86/pr18162.ll Normal file
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@@ -0,0 +1,27 @@
; RUN: llc < %s
; Make sure we are not crashing on this one.
target triple = "x86_64-unknown-linux-gnu"
%"Iterator" = type { i32* }
declare { i64, <2 x float> } @Call()
declare { i64, <2 x float> }* @CallPtr()
define { i64, <2 x float> } @Foo(%"Iterator"* %this) {
entry:
%retval = alloca i32
%this.addr = alloca %"Iterator"*
%this1 = load %"Iterator"** %this.addr
%bundle_ = getelementptr inbounds %"Iterator"* %this1, i32 0, i32 0
%0 = load i32** %bundle_
%1 = call { i64, <2 x float> } @Call()
%2 = call { i64, <2 x float> }* @CallPtr()
%3 = getelementptr { i64, <2 x float> }* %2, i32 0, i32 1
%4 = extractvalue { i64, <2 x float> } %1, 1
store <2 x float> %4, <2 x float>* %3
%5 = load { i64, <2 x float> }* %2
ret { i64, <2 x float> } %5
}