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Unify selectMipsCPU implementations.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229595 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Eric Christopher 2015-02-18 00:55:06 +00:00
parent 0afc9b33fe
commit 68499a2f20
3 changed files with 11 additions and 20 deletions
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4
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp
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@ -43,7 +43,7 @@ using namespace llvm;
/// Select the Mips CPU for the given triple and cpu name. /// Select the Mips CPU for the given triple and cpu name.
/// FIXME: Merge with the copy in MipsSubtarget.cpp /// FIXME: Merge with the copy in MipsSubtarget.cpp
static inline StringRef selectMipsCPU(StringRef TT, StringRef CPU) { StringRef MIPS_MC::selectMipsCPU(StringRef TT, StringRef CPU) {
if (CPU.empty() || CPU == "generic") { if (CPU.empty() || CPU == "generic") {
Triple TheTriple(TT); Triple TheTriple(TT);
if (TheTriple.getArch() == Triple::mips || if (TheTriple.getArch() == Triple::mips ||
@ -69,7 +69,7 @@ static MCRegisterInfo *createMipsMCRegisterInfo(StringRef TT) {
static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU, static MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
StringRef FS) { StringRef FS) {
CPU = selectMipsCPU(TT, CPU); CPU = MIPS_MC::selectMipsCPU(TT, CPU);
MCSubtargetInfo *X = new MCSubtargetInfo(); MCSubtargetInfo *X = new MCSubtargetInfo();
InitMipsMCSubtargetInfo(X, TT, CPU, FS); InitMipsMCSubtargetInfo(X, TT, CPU, FS);
return X; return X;

11
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.h
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@ -55,10 +55,13 @@ MCAsmBackend *createMipsAsmBackendEL64(const Target &T,
const MCRegisterInfo &MRI, StringRef TT, const MCRegisterInfo &MRI, StringRef TT,
StringRef CPU); StringRef CPU);
MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, MCObjectWriter *createMipsELFObjectWriter(raw_ostream &OS, uint8_t OSABI,
uint8_t OSABI, bool IsLittleEndian, bool Is64Bit);
bool IsLittleEndian,
bool Is64Bit); namespace MIPS_MC {
StringRef selectMipsCPU(StringRef TT, StringRef CPU);
}
} // End llvm namespace } // End llvm namespace
// Defines symbolic names for Mips registers. This defines a mapping from // Defines symbolic names for Mips registers. This defines a mapping from

16
lib/Target/Mips/MipsSubtarget.cpp
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@ -143,23 +143,11 @@ CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
return CodeGenOpt::Aggressive; return CodeGenOpt::Aggressive;
} }
/// Select the Mips CPU for the given triple and cpu name.
/// FIXME: Merge with the copy in MipsMCTargetDesc.cpp
static StringRef selectMipsCPU(Triple TT, StringRef CPU) {
if (CPU.empty() || CPU == "generic") {
if (TT.getArch() == Triple::mips || TT.getArch() == Triple::mipsel)
CPU = "mips32";
else
CPU = "mips64";
}
return CPU;
}
MipsSubtarget & MipsSubtarget &
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS, MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
const TargetMachine &TM) { const TargetMachine &TM) {
std::string CPUName = selectMipsCPU(TargetTriple, CPU); std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
// Parse features string. // Parse features string.
ParseSubtargetFeatures(CPUName, FS); ParseSubtargetFeatures(CPUName, FS);
// Initialize scheduling itinerary for the specified CPU. // Initialize scheduling itinerary for the specified CPU.