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Generate slightly smaller code, "test R, R" instead of "cmp R, 0"

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12579 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-03-31 22:22:36 +00:00
parent 08bde1870a
commit 68626c2b30
2 changed files with 6 additions and 10 deletions
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8
lib/Target/X86/InstSelectSimple.cpp
View File

@ -1015,8 +1015,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
CondReg = X86::BL; CondReg = X86::BL;
} }
// FIXME: Should generate a 'tst r, r' BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
Opcode = X86::FCMOVE; Opcode = X86::FCMOVE;
} }
break; break;
@ -1047,8 +1046,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
} else { } else {
// Get the value being branched on, and use it to set the condition codes. // Get the value being branched on, and use it to set the condition codes.
unsigned CondReg = getReg(Cond, MBB, IP); unsigned CondReg = getReg(Cond, MBB, IP);
// FIXME: Should generate a 'tst r, r' BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
switch (SelectClass) { switch (SelectClass) {
default: assert(0 && "Unknown value class!"); default: assert(0 && "Unknown value class!");
case cFP: Opcode = X86::FCMOVE; break; case cFP: Opcode = X86::FCMOVE; break;
@ -1209,7 +1207,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
// Nope, cannot fold setcc into this branch. Emit a branch on a condition // Nope, cannot fold setcc into this branch. Emit a branch on a condition
// computed some other way... // computed some other way...
unsigned condReg = getReg(BI.getCondition()); unsigned condReg = getReg(BI.getCondition());
BuildMI(BB, X86::CMP8ri, 2).addReg(condReg).addImm(0); BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
if (BI.getSuccessor(1) == NextBB) { if (BI.getSuccessor(1) == NextBB) {
if (BI.getSuccessor(0) != NextBB) if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0)); BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));

8
lib/Target/X86/X86ISelSimple.cpp
View File

@ -1015,8 +1015,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
CondReg = X86::BL; CondReg = X86::BL;
} }
// FIXME: Should generate a 'tst r, r' BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
Opcode = X86::FCMOVE; Opcode = X86::FCMOVE;
} }
break; break;
@ -1047,8 +1046,7 @@ void ISel::emitSelectOperation(MachineBasicBlock *MBB,
} else { } else {
// Get the value being branched on, and use it to set the condition codes. // Get the value being branched on, and use it to set the condition codes.
unsigned CondReg = getReg(Cond, MBB, IP); unsigned CondReg = getReg(Cond, MBB, IP);
// FIXME: Should generate a 'tst r, r' BuildMI(*MBB, IP, X86::TEST8rr, 2).addReg(CondReg).addReg(CondReg);
BuildMI(*MBB, IP, X86::CMP8ri, 2).addReg(CondReg).addImm(0);
switch (SelectClass) { switch (SelectClass) {
default: assert(0 && "Unknown value class!"); default: assert(0 && "Unknown value class!");
case cFP: Opcode = X86::FCMOVE; break; case cFP: Opcode = X86::FCMOVE; break;
@ -1209,7 +1207,7 @@ void ISel::visitBranchInst(BranchInst &BI) {
// Nope, cannot fold setcc into this branch. Emit a branch on a condition // Nope, cannot fold setcc into this branch. Emit a branch on a condition
// computed some other way... // computed some other way...
unsigned condReg = getReg(BI.getCondition()); unsigned condReg = getReg(BI.getCondition());
BuildMI(BB, X86::CMP8ri, 2).addReg(condReg).addImm(0); BuildMI(BB, X86::TEST8rr, 2).addReg(condReg).addReg(condReg);
if (BI.getSuccessor(1) == NextBB) { if (BI.getSuccessor(1) == NextBB) {
if (BI.getSuccessor(0) != NextBB) if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0)); BuildMI(BB, X86::JNE, 1).addPCDisp(BI.getSuccessor(0));