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Make the type of shift amount i32 in order to reduce the number of shift
instruction definitions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143989 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -32,7 +32,7 @@ def Subtract32 : SDNodeXForm<imm, [{
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def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>;
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// imm32_63 predicate - True if imm is in range [32, 63].
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def imm32_63 : ImmLeaf<i64,
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def imm32_63 : ImmLeaf<i32,
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[{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
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Subtract32>;
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@ -43,12 +43,12 @@ def imm32_63 : ImmLeaf<i64,
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// 64-bit shift instructions.
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class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
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SDNode OpNode>:
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shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5_64, shamt_64,
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shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt,
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CPU64Regs>;
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class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
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SDNode OpNode>:
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shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt_64,
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shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt,
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CPU64Regs>;
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// Mul, Div
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@ -98,6 +98,8 @@ namespace llvm {
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public:
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explicit MipsTargetLowering(MipsTargetMachine &TM);
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virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
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virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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@ -327,9 +327,9 @@ class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
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class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
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SDNode OpNode, RegisterClass RC>:
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FR<0x00, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
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FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
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!strconcat(instr_asm, "\t$rd, $rt, $rs"),
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[(set RC:$rd, (OpNode RC:$rt, RC:$rs))], IIAlu> {
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[(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
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let shamt = isRotate;
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}
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