6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-17 21:35:07 +00:00
Code Issues Projects Releases Wiki Activity

Make the type of shift amount i32 in order to reduce the number of shift

Browse Source 
instruction definitions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143989 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-11-07 18:59:49 +00:00
parent bce22b48fe
commit 68698cc20d
3 changed files with 7 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -32,7 +32,7 @@ def Subtract32 : SDNodeXForm<imm, [{
def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>; def immZExt5_64 : ImmLeaf<i64, [{return Imm == (Imm & 0x1f);}]>;
// imm32_63 predicate - True if imm is in range [32, 63]. // imm32_63 predicate - True if imm is in range [32, 63].
def imm32_63 : ImmLeaf<i64, def imm32_63 : ImmLeaf<i32,
[{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}], [{return (int32_t)Imm >= 32 && (int32_t)Imm < 64;}],
Subtract32>; Subtract32>;
@ -43,12 +43,12 @@ def imm32_63 : ImmLeaf<i64,
// 64-bit shift instructions. // 64-bit shift instructions.
class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm, class shift_rotate_imm64<bits<6> func, bits<5> isRotate, string instr_asm,
SDNode OpNode>: SDNode OpNode>:
shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5_64, shamt_64, shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt,
CPU64Regs>; CPU64Regs>;
class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm, class shift_rotate_imm64_32<bits<6> func, bits<5> isRotate, string instr_asm,
SDNode OpNode>: SDNode OpNode>:
shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt_64, shift_rotate_imm<func, isRotate, instr_asm, OpNode, imm32_63, shamt,
CPU64Regs>; CPU64Regs>;
// Mul, Div // Mul, Div

2
lib/Target/Mips/MipsISelLowering.h
View File

@ -98,6 +98,8 @@ namespace llvm {
public: public:
explicit MipsTargetLowering(MipsTargetMachine &TM); explicit MipsTargetLowering(MipsTargetMachine &TM);
virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
virtual bool allowsUnalignedMemoryAccesses (EVT VT) const; virtual bool allowsUnalignedMemoryAccesses (EVT VT) const;
/// LowerOperation - Provide custom lowering hooks for some operations. /// LowerOperation - Provide custom lowering hooks for some operations.

4
lib/Target/Mips/MipsInstrInfo.td
View File

@ -327,9 +327,9 @@ class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm, class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
SDNode OpNode, RegisterClass RC>: SDNode OpNode, RegisterClass RC>:
FR<0x00, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rd, $rt, $rs"), !strconcat(instr_asm, "\t$rd, $rt, $rs"),
[(set RC:$rd, (OpNode RC:$rt, RC:$rs))], IIAlu> { [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
let shamt = isRotate; let shamt = isRotate;
} }