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[mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copy

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physical register $r1 to $r0.

GNU disassembler recognizes an "or" instruction as a "move", and this change
makes the disassembled code easier to read.

Original patch by Reed Kotler.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170655 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
2012-12-20 04:06:06 +00:00
parent ba836a2e80
commit 68fe665b9a
7 changed files with 23 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
lib/Target/Mips/MipsSEInstrInfo.cpp
View File

@@ -90,7 +90,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
if (Mips::CPURegsRegClass.contains(SrcReg))
Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
Opc = Mips::OR, ZeroReg = Mips::ZERO;
else if (Mips::CCRRegClass.contains(SrcReg))
Opc = Mips::CFC1;
else if (Mips::FGR32RegClass.contains(SrcReg))
@@ -120,7 +120,7 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Opc = Mips::MOVCCRToCCR;
else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
if (Mips::CPU64RegsRegClass.contains(SrcReg))
Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
else if (SrcReg == Mips::HI64)
Opc = Mips::MFHI64, SrcReg = 0;
else if (SrcReg == Mips::LO64)
@@ -144,11 +144,11 @@ void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
if (DestReg)
MIB.addReg(DestReg, RegState::Define);
if (ZeroReg)
MIB.addReg(ZeroReg);
if (SrcReg)
MIB.addReg(SrcReg, getKillRegState(KillSrc));
if (ZeroReg)
MIB.addReg(ZeroReg);
}
void MipsSEInstrInfo::

10
test/CodeGen/Mips/alloca.ll
View File

@@ -3,11 +3,11 @@
define i32 @twoalloca(i32 %size) nounwind {
entry:
; CHECK: subu $[[T0:[0-9]+]], $sp, $[[SZ:[0-9]+]]
; CHECK: addu $sp, $zero, $[[T0]]
; CHECK: or $sp, $[[T0]], $zero
; CHECK: subu $[[T2:[0-9]+]], $sp, $[[SZ]]
; CHECK: addu $sp, $zero, $[[T2]]
; CHECK: addu $4, $zero, $[[T0]]
; CHECK: addu $4, $zero, $[[T2]]
; CHECK: or $sp, $[[T2]], $zero
; CHECK: or $4, $[[T0]], $zero
; CHECK: or $4, $[[T2]], $zero
%tmp1 = alloca i8, i32 %size, align 4
%add.ptr = getelementptr inbounds i8* %tmp1, i32 5
store i8 97, i8* %add.ptr, align 1
@@ -29,7 +29,7 @@ define i32 @alloca2(i32 %size) nounwind {
entry:
; CHECK: alloca2
; CHECK: subu $[[T0:[0-9]+]], $sp
; CHECK: addu $sp, $zero, $[[T0]]
; CHECK: or $sp, $[[T0]], $zero
%tmp1 = alloca i8, i32 %size, align 4
%0 = bitcast i8* %tmp1 to i32*

2
test/CodeGen/Mips/frame-address.ll
View File

@@ -8,5 +8,5 @@ entry:
ret i8* %0
; CHECK: addu $fp, $sp, $zero
; CHECK: addu $2, $zero, $fp
; CHECK: or $2, $fp, $zero
}

4
test/CodeGen/Mips/gpreg-lazy-binding.ll
View File

@@ -2,10 +2,10 @@
@g = external global i32
; CHECK: addu $gp
; CHECK: or $gp
; CHECK: jalr $25
; CHECK: nop
; CHECK-NOT: addu $gp
; CHECK-NOT: or $gp
; CHECK: jalr $25
define void @f0() nounwind {

12
test/CodeGen/Mips/i64arg.ll
View File

@@ -2,8 +2,8 @@
define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind {
entry:
; CHECK: addu $[[R1:[0-9]+]], $zero, $5
; CHECK: addu $[[R0:[0-9]+]], $zero, $4
; CHECK: or $[[R1:[0-9]+]], $5, $zero
; CHECK: or $[[R0:[0-9]+]], $4, $zero
; CHECK: ori $6, ${{[0-9]+}}, 3855
; CHECK: ori $7, ${{[0-9]+}}, 22136
; CHECK: lw $25, %call16(ff1)
@@ -12,16 +12,16 @@ entry:
; CHECK: lw $25, %call16(ff2)
; CHECK: lw $[[R2:[0-9]+]], 80($sp)
; CHECK: lw $[[R3:[0-9]+]], 84($sp)
; CHECK: addu $4, $zero, $[[R2]]
; CHECK: addu $5, $zero, $[[R3]]
; CHECK: or $4, $[[R2]], $zero
; CHECK: or $5, $[[R3]], $zero
; CHECK: jalr $25
tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind
%sub = add nsw i32 %i, -1
; CHECK: sw $[[R1]], 28($sp)
; CHECK: sw $[[R0]], 24($sp)
; CHECK: lw $25, %call16(ff3)
; CHECK: addu $6, $zero, $[[R2]]
; CHECK: addu $7, $zero, $[[R3]]
; CHECK: or $6, $[[R2]], $zero
; CHECK: or $7, $[[R3]], $zero
; CHECK: jalr $25
tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind
ret void

2
test/CodeGen/Mips/mips64-sret.ll
View File

@@ -6,7 +6,7 @@
define void @f(%struct.S* noalias sret %agg.result) nounwind {
entry:
; CHECK: daddu $2, $zero, $4
; CHECK: or $2, $4, $zero
%0 = bitcast %struct.S* %agg.result to i8*
call void @llvm.memcpy.p0i8.p0i8.i64(i8* %0, i8* bitcast (%struct.S* @g to i8*), i64 32, i32 4, i1 false)

6
test/CodeGen/Mips/return_address.ll
View File

@@ -5,7 +5,7 @@ entry:
%0 = call i8* @llvm.returnaddress(i32 0)
ret i8* %0
; CHECK: addu $2, $zero, $ra
; CHECK: or $2, $ra, $zero
}
define i8* @f2() nounwind {
@@ -14,9 +14,9 @@ entry:
%0 = call i8* @llvm.returnaddress(i32 0)
ret i8* %0
; CHECK: addu $[[R0:[0-9]+]], $zero, $ra
; CHECK: or $[[R0:[0-9]+]], $ra, $zero
; CHECK: jal
; CHECK: addu $2, $zero, $[[R0]]
; CHECK: or $2, $[[R0]], $zero
}
declare i8* @llvm.returnaddress(i32) nounwind readnone