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[Hexagon] Remove dead constant assignment in hardware loop pass

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After converting a loop to a hardware loop, the pass should remove
any unnecessary instructions from the old compare-and-branch
code. This patch removes a dead constant assignment that was
used in the compare instruction.

Differential Revision: http://reviews.llvm.org/D9720


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237373 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brendon Cahoon 2015-05-14 17:31:40 +00:00
parent c2c3c689e6
commit 6912fe6f35
2 changed files with 32 additions and 3 deletions
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12
lib/Target/Hexagon/HexagonHardwareLoops.cpp
View File

@ -670,6 +670,7 @@ CountValue *HexagonHardwareLoops::getLoopTripCount(MachineLoop *L,
MachineBasicBlock *DefBB = MRI->getVRegDef(R)->getParent();
if (!MDT->properlyDominates(DefBB, Header))
return nullptr;
OldInsts.push_back(MRI->getVRegDef(R));
}
return computeCount(L, InitialValue, EndValue, IVReg, IVBump, Cmp);
@ -693,12 +694,14 @@ CountValue *HexagonHardwareLoops::computeCount(MachineLoop *Loop,
// If so, use the immediate value rather than the register.
if (Start->isReg()) {
const MachineInstr *StartValInstr = MRI->getVRegDef(Start->getReg());
if (StartValInstr && StartValInstr->getOpcode() == Hexagon::A2_tfrsi)
if (StartValInstr && (StartValInstr->getOpcode() == Hexagon::A2_tfrsi ||
StartValInstr->getOpcode() == Hexagon::A2_tfrpi))
Start = &StartValInstr->getOperand(1);
}
if (End->isReg()) {
const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
if (EndValInstr && EndValInstr->getOpcode() == Hexagon::A2_tfrsi)
if (EndValInstr && (EndValInstr->getOpcode() == Hexagon::A2_tfrsi ||
EndValInstr->getOpcode() == Hexagon::A2_tfrpi))
End = &EndValInstr->getOperand(1);
}
@ -1832,11 +1835,14 @@ MachineBasicBlock *HexagonHardwareLoops::createPreheaderForLoop(
// created PHI node in the preheader.
for (unsigned i = 1, n = PN->getNumOperands(); i < n; i += 2) {
unsigned PredR = PN->getOperand(i).getReg();
unsigned PredRSub = PN->getOperand(i).getSubReg();
MachineBasicBlock *PredB = PN->getOperand(i+1).getMBB();
if (PredB == Latch)
continue;
NewPN->addOperand(MachineOperand::CreateReg(PredR, false));
MachineOperand MO = MachineOperand::CreateReg(PredR, false);
MO.setSubReg(PredRSub);
NewPN->addOperand(MO);
NewPN->addOperand(MachineOperand::CreateMBB(PredB));
}

23
test/CodeGen/Hexagon/hwloop-ph-deadcode.ll Normal file
View File

@ -0,0 +1,23 @@
; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 -disable-block-placement=0 < %s | FileCheck %s
; Test that there is no redundant register assignment in the hardware loop
; preheader.
; CHECK-NOT: r{{.*}} = #5
@g = external global i32
define void @foo() #0 {
entry:
br i1 undef, label %if.end38, label %for.body
for.body:
%loopIdx.051 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
store i32 1, i32* @g, align 4
%inc = add i32 %loopIdx.051, 1
%cmp9 = icmp ult i32 %inc, 5
br i1 %cmp9, label %for.body, label %if.end38
if.end38:
ret void
}