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Small cleanups. No functionality change intended!

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58992 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Duncan Sands 2008-11-10 17:29:56 +00:00
parent a29c13086a
commit 6959b2bb65
3 changed files with 13 additions and 16 deletions
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5
include/llvm/CodeGen/ValueTypes.h
View File

@ -272,6 +272,11 @@ namespace llvm {
return BitSize >= 8 && !(BitSize & (BitSize - 1));
}
/// bitsEq - Return true if this has the same number of bits as VT.
bool bitsEq(MVT VT) const {
return getSizeInBits() == VT.getSizeInBits();
}
/// bitsGT - Return true if this has more bits than VT.
bool bitsGT(MVT VT) const {
return getSizeInBits() > VT.getSizeInBits();

22
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -206,7 +206,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
case Legal:
break;
case PromoteInteger:
if (OutVT.getSizeInBits() == NInVT.getSizeInBits())
if (OutVT.bitsEq(NInVT))
// The input promotes to the same size. Convert the promoted value.
return DAG.getNode(ISD::BIT_CONVERT, OutVT, GetPromotedInteger(InOp));
break;
@ -340,8 +340,8 @@ SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
// Hi if it was odd.
SDValue Lo = Elt;
SDValue Hi = DAG.getNode(ISD::SRL, NewVT, Elt,
DAG.getConstant(OldVT.getSizeInBits(),
TLI.getShiftAmountTy()));
DAG.getConstant(OldVT.getSizeInBits(),
TLI.getShiftAmountTy()));
if (TLI.isBigEndian())
std::swap(Lo, Hi);
@ -378,8 +378,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
SDValue Res = GetPromotedInteger(N->getOperand(0));
assert(Res.getValueType().getSizeInBits() <= NVT.getSizeInBits() &&
"Extension doesn't make sense!");
assert(Res.getValueType().bitsLE(NVT) && "Extension doesn't make sense!");
// If the result and operand types are the same after promotion, simplify
// to an in-register extension.
@ -451,8 +450,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
// Convert to the expected type.
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(NVT.getSizeInBits() <= SVT.getSizeInBits() &&
"Integer type overpromoted?");
assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
return DAG.getNode(ISD::TRUNCATE, NVT, SetCC);
}
@ -494,6 +492,7 @@ SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
}
SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Res;
switch (getTypeAction(N->getOperand(0).getValueType())) {
@ -507,12 +506,6 @@ SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
break;
}
MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(Res.getValueType().getSizeInBits() >= NVT.getSizeInBits() &&
"Truncation doesn't make sense!");
if (Res.getValueType() == NVT)
return Res;
// Truncate to NVT instead of VT
return DAG.getNode(ISD::TRUNCATE, NVT, Res);
}
@ -845,8 +838,7 @@ SDValue DAGTypeLegalizer::PromoteIntOp_SELECT(SDNode *N, unsigned OpNo) {
// around the problem.
MVT SVT = TLI.getSetCCResultType(N->getOperand(1));
assert(isTypeLegal(SVT) && "Illegal SetCC type!");
assert(Cond.getValueSizeInBits() <= SVT.getSizeInBits() &&
"Unexpected SetCC type!");
assert(Cond.getValueType().bitsLE(SVT) && "Unexpected SetCC type!");
// Make sure the extra bits conform to getSetCCResultContents. There are
// two sets of extra bits: those in Cond, which come from type promotion,

2
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
View File

@ -191,7 +191,7 @@ SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
// VSETCC always returns a sign-extended value, while SETCC may not. The
// SETCC result type may not match the vector element type. Correct these.
if (NVT.getSizeInBits() <= SVT.getSizeInBits()) {
if (NVT.bitsLE(SVT)) {
// The SETCC result type is bigger than the vector element type.
// Ensure the SETCC result is sign-extended.
if (TLI.getSetCCResultContents() !=