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Significantly improve Atomic.h by pulling in code from libatomic_ops by HP. This is a little outdated, but reasonably complete.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@71973 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Owen Anderson
parent
de52f865b6
commit
6962815683
@ -67,3 +67,4 @@ Autoconf llvm/autoconf
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llvm/projects/sample/autoconf
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CellSPU backend llvm/lib/Target/CellSPU/README.txt
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Google Test llvm/utils/unittest/googletest
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Atomics Library llvm/include/llvm/System/Atomic.h
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@ -9,6 +9,29 @@
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//
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// This file declares the llvm::sys atomic operations.
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//
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// Portions of this file use code from libatomic_ops, for which the following
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// license applies:
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//
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// Copyright (c) 2003 by Hewlett-Packard Company. All rights reserved.
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy
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// of this software and associated documentation files (the "Software"), to deal
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// in the Software without restriction, including without limitation the rights
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// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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// copies of the Software, and to permit persons to whom the Software is
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// furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in
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// all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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// SOFTWARE.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_SYSTEM_ATOMIC_H
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@ -16,21 +39,33 @@
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#include <stdint.h>
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#if defined(__APPLE__)
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#if __GNUC__ < 4 || (__GNUC__ == 4 && __GNUC_MINOR__ == 0)
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#include <libkern/OSAtomic.h>
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#endif
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#elif LLVM_ON_WIN32
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#if defined(_HPUX_SOURCE) && defined(__ia64)
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#include <machine/sys/inline.h>
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#elif defined(_MSC_VER)
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#include <windows.h>
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#endif
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#endif // defined(_HPUX_SOURCE) && defined(__ia64)
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namespace llvm {
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namespace sys {
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inline void CompilerFence() {
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#if defined(__GNUC__) && !defined(__INTEL_COMPILER)
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__asm__ __volatile__("" : : : "memory");
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#elif defined(_MSC_VER)
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__asm { };
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#elif defined(__INTEL_COMPILER)
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__memory_barrier(); /* Too strong? IA64-only? */
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#else
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/* We conjecture that the following usually gives us the right */
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/* semantics or an error. */
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asm("");
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#endif // defined(__GNUC__) && !defined(__INTEL_COMPILER)
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}
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#if !defined(ENABLE_THREADS) || ENABLE_THREADS == 0
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inline void MemoryFence() {
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return;
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CompilerFence();
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}
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typedef uint32_t cas_flag;
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@ -41,47 +76,130 @@ namespace llvm {
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return result;
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}
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#elif __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 1)
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#elif defined(__GNUC__)
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inline void MemoryFence() {
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__sync_synchronize();
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# if defined(__i386__) || defined(__x86_64__)
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# if defined(__SSE2__)
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__asm__ __volatile__("mfence" : : : "memory");
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# else
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unsigned char dummy = 0;
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volatile unsigned char* addr = &dummy;
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unsigned char oldval;
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__asm __ __volatile__("xchgb %0, %1" : "=r"(oldval),
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"=m"(*addr), "0"(0xff), "m"(*addr) : "memory");
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# endif // defined(__SSE2__)
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# elif defined(__ia64__)
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__asm__ __volatile__("mf" : : : "memory");
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# elif defined(__alpha__)
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__asm__ __volatile__("mb" : : : "memory");
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# elif defined(__sparc__)
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__asm__ __volatile__("membar #StoreStore | #LoadStore | #LoadLoad | #StoreLoad");
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# elif defined(__powerpc__) || defined(__ppc__)
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__asm__ __volatile__("sync" : : : "memory");
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# elif defined(__arm__)
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__asm__ __volatile__ ("mcr p15, 0, r0, c7, c10, 5 @ dmb");
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# endif
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} // defined(__i386__) || defined(__x86_64__)
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typedef unsigned long cas_flag;
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inline cas_flag CompareAndSwap(cas_flag* ptr,
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cas_flag new_value,
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cas_flag old_value) {
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cas_flag prev;
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# if defined(__i386__) || defined(__x86_64__)
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__asm__ __volatile__("lock; cmpxchgl %1,%2"
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: "=a" (prev)
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: "q" (new_value), "m" (*ptr), "0" (old_value)
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: "memory");
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# elif defined(__ia64__)
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MemoryFence();
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# if defined(_ILP32)
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__asm__("zxt4 %1=%1": "=r"(prev) : "0"(prev));
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__asm__ __volatile__("addp4 %1=0,%1;;\n"
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"mov ar.ccv=%[old] ;; cmpxchg 4"
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".acq %0=[%1],%[new_val],ar.ccv"
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: "=r"(prev) "1"(addr),
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: "=r"(addr), [new_value]"r"(new_value), [old_value]"r"(old_value)
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: "memory");
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# else
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__asm__ __volatile__(
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"mov ar.ccv=%[old] ;; cmpxchg 8"
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".acq %0=[%1],%[new_val],ar.ccv"
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: "=r"(prev)
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: "r"(ptr), [new_value]"r"(new_value),
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[old_value]"r"(old_value)
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: "memory");
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# endif // defined(_ILP32)
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# elif defined(__alpha__)
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cas_flag was_equal;
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__asm__ __volatile__(
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"1: ldq_l %0,%1\n"
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" cmpeq %0,%4,%2\n"
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" mov %3,%0\n"
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" beq %2,2f\n"
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" stq_c %0,%1\n"
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" beq %0,1b\n"
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"2:\n"
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:"=&r" (prev), "=m" (*ptr), "=&r" (was_equal)
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: "r" (new_value), "Ir" (old_value)
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:"memory");
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#elif defined(__sparc__)
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#error No CAS implementation for SPARC yet.
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#elif defined(__powerpc__) || defined(__ppc__)
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int result = 0;
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__asm__ __volatile__(
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"1:lwarx %0,0,%2\n" /* load and reserve */
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"cmpw %0, %4\n" /* if load is not equal to */
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"bne 2f\n" /* old, fail */
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"stwcx. %3,0,%2\n" /* else store conditional */
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"bne- 1b\n" /* retry if lost reservation */
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"li %1,1\n" /* result = 1; */
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"2:\n"
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: "=&r"(prev), "=&r"(result)
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: "r"(ptr), "r"(new_value), "r"(old_value), "1"(result)
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: "memory", "cc");
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#elif defined(__arm__)
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int result;
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__asm__ __volatile__ (
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"\n"
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"0:\t"
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"ldr %1,[%2] \n\t"
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"mov %0,#0 \n\t"
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"cmp %1,%4 \n\t"
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"bne 1f \n\t"
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"swp %0,%3,[%2] \n\t"
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"cmp %1,%0 \n\t"
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"swpne %1,%0,[%2] \n\t"
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"bne 0b \n\t"
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"mov %0,#1 \n"
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"1:\n\t"
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""
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: "=&r"(result), "=&r"(prev)
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: "r" ptr), "r" (new_value), "r" (old_value)
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: "cc", "memory");
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#endif // defined(__i386__)
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return prev;
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}
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typedef uint32_t cas_flag;
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inline cas_flag CompareAndSwap(cas_flag* dest, cas_flag exc, cas_flag c) {
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return __sync_val_compare_and_swap(dest, exc, c);
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}
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#elif defined(__APPLE__)
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#elif defined(_MSC_VER) && _M_IX86 > 400
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inline void MemoryFence() {
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OSMemoryBarrier();
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LONG dummy = 0;
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InterlockedExchanged((LONG volatile *)&dummy, (LONG)0);
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}
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typedef int32_t cas_flag;
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inline cas_flag CompareAndSwap(cas_flag* dest, cas_flag exc, cas_flag c) {
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cas_flag old = *dest;
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OSAtomicCompareAndSwap32(c, exc, dest);
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return old;
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}
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#elif defined(LLVM_ON_WIN32)
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inline void MemoryFence() {
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#ifdef _MSC_VER
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MemoryBarrier();
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#elif 0
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// FIXME: Requires SSE2 support
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__asm__ __volatile__("mfence":::"memory");
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#else
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// FIXME: just temporary workaround. We need to emit some fence...
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__asm__ __volatile__("":::"memory");
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#endif
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}
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typedef volatile long cas_flag;
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inline cas_flag CompareAndSwap(cas_flag* dest, cas_flag exc, cas_flag c) {
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return InterlockedCompareExchange(dest, exc, c);
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typedef DWORD cas_flag;
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inline cas_flag CompareAndSwap(cas_flag* ptr,
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cas_flag new_value,
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cas_flag old_value) {
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/* FIXME - This is nearly useless on win64. */
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/* Use InterlockedCompareExchange64 for win64? */
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return InterlockedCompareExchange((DWORD volatile *)addr,
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(DWORD)new_value, (DWORD) old_value)
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}
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#else
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#error No memory atomics implementation for your platform!
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#endif
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#error No atomics implementation found for your platform.
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#endif // !defined(ENABLE_THREADS) || ENABLE_THREADS == 0
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}
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}
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