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Added sub- register classes information.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28196 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -47,14 +47,18 @@ public:
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typedef const unsigned* const_iterator;
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typedef const MVT::ValueType* vt_iterator;
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typedef const TargetRegisterClass** sc_iterator;
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private:
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const vt_iterator VTs;
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const sc_iterator SubClasses;
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const unsigned RegSize, Alignment; // Size & Alignment of register in bytes
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const iterator RegsBegin, RegsEnd;
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public:
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TargetRegisterClass(const MVT::ValueType *vts, unsigned RS, unsigned Al,
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iterator RB, iterator RE)
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: VTs(vts), RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
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TargetRegisterClass(const MVT::ValueType *vts,
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const TargetRegisterClass **scs,
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unsigned RS, unsigned Al, iterator RB, iterator RE)
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: VTs(vts), SubClasses(scs),
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RegSize(RS), Alignment(Al), RegsBegin(RB), RegsEnd(RE) {}
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virtual ~TargetRegisterClass() {} // Allow subclasses
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// begin/end - Return all of the registers in this class.
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@ -87,20 +91,38 @@ public:
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return false;
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}
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/// vt_begin - Loop over all of the value types that can be represented by
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/// values in this register class.
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/// vt_begin / vt_end - Loop over all of the value types that can be
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/// represented by values in this register class.
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vt_iterator vt_begin() const {
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return VTs;
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}
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/// vt_begin - Loop over all of the value types that can be represented by
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/// values in this register class.
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vt_iterator vt_end() const {
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vt_iterator I = VTs;
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while (*I != MVT::Other) ++I;
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return I;
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}
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/// hasSubRegClass - return true if the specified TargetRegisterClass is a
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/// sub-register class of this TargetRegisterClass.
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bool hasSubRegClass(const TargetRegisterClass *cs) const {
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for (int i = 0; SubClasses[i] != NULL; ++i)
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if (SubClasses[i] == cs)
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return true;
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return false;
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}
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/// subclasses_begin / subclasses_end - Loop over all of the sub-classes of
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/// this register class.
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sc_iterator subclasses_begin() const {
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return SubClasses;
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}
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sc_iterator subclasses_end() const {
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sc_iterator I = SubClasses;
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while (*I != NULL) ++I;
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return I;
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}
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/// allocation_order_begin/end - These methods define a range of registers
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/// which specify the registers in this class that are valid to register
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