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maintain LiveIn when splitting blocks (register scavenging needs it)

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35226 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Dale Johannesen
2007-03-20 21:35:06 +00:00
parent cbdfb8a9d5
commit 69cb9b78f1
3 changed files with 32 additions and 1 deletions
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3
include/llvm/CodeGen/RegisterScavenging.h
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@@ -91,6 +91,9 @@ public:
bool isUsed(unsigned Reg) const { return !RegStates[Reg]; } bool isUsed(unsigned Reg) const { return !RegStates[Reg]; }
bool isUnused(unsigned Reg) const { return RegStates[Reg]; } bool isUnused(unsigned Reg) const { return RegStates[Reg]; }
/// getRegsUsed - return all registers currently in use in used.
void getRegsUsed(BitVector &used, bool includeReserved);
/// setUsed / setUnused - Mark the state of one or a number of registers. /// setUsed / setUnused - Mark the state of one or a number of registers.
/// ///
void setUsed(unsigned Reg) { RegStates.reset(Reg); } void setUsed(unsigned Reg) { RegStates.reset(Reg); }

21
lib/CodeGen/BranchFolding.cpp
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@@ -21,8 +21,10 @@
#include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineJumpTableInfo.h" #include "llvm/CodeGen/MachineJumpTableInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
#include "llvm/Target/TargetInstrInfo.h" #include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h" #include "llvm/Target/TargetMachine.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Support/CommandLine.h" #include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
@@ -50,6 +52,8 @@ namespace {
MachineBasicBlock *SplitMBBAt(MachineBasicBlock &CurMBB, MachineBasicBlock *SplitMBBAt(MachineBasicBlock &CurMBB,
MachineBasicBlock::iterator BBI1); MachineBasicBlock::iterator BBI1);
const MRegisterInfo *RegInfo;
RegScavenger *RS;
// Branch optzn. // Branch optzn.
bool OptimizeBranches(MachineFunction &MF); bool OptimizeBranches(MachineFunction &MF);
void OptimizeBlock(MachineBasicBlock *MBB); void OptimizeBlock(MachineBasicBlock *MBB);
@@ -95,6 +99,9 @@ bool BranchFolder::runOnMachineFunction(MachineFunction &MF) {
TII = MF.getTarget().getInstrInfo(); TII = MF.getTarget().getInstrInfo();
if (!TII) return false; if (!TII) return false;
RegInfo = MF.getTarget().getRegisterInfo();
RS = RegInfo->requiresRegisterScavenging(MF) ? new RegScavenger() : NULL;
MMI = getAnalysisToUpdate<MachineModuleInfo>(); MMI = getAnalysisToUpdate<MachineModuleInfo>();
bool EverMadeChange = false; bool EverMadeChange = false;
@@ -153,6 +160,7 @@ bool BranchFolder::runOnMachineFunction(MachineFunction &MF) {
} }
} }
delete RS;
return EverMadeChange; return EverMadeChange;
} }
@@ -280,6 +288,19 @@ MachineBasicBlock *BranchFolder::SplitMBBAt(MachineBasicBlock &CurMBB,
// Splice the code over. // Splice the code over.
NewMBB->splice(NewMBB->end(), &CurMBB, BBI1, CurMBB.end()); NewMBB->splice(NewMBB->end(), &CurMBB, BBI1, CurMBB.end());
// For targets that use the register scavenger, we must maintain LiveIns.
if (RS) {
RS->enterBasicBlock(&CurMBB);
if (!CurMBB.empty())
RS->forward(prior(CurMBB.end()));
BitVector RegsLiveAtExit(RegInfo->getNumRegs());
RS->getRegsUsed(RegsLiveAtExit, false);
for (unsigned int i=0, e=RegInfo->getNumRegs(); i!=e; i++)
if (RegsLiveAtExit[i])
NewMBB->addLiveIn(i);
}
return NewMBB; return NewMBB;
} }

7
lib/CodeGen/RegisterScavenging.cpp
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@@ -180,6 +180,13 @@ void RegScavenger::backward() {
setUsed(ChangedRegs); setUsed(ChangedRegs);
} }
void RegScavenger::getRegsUsed(BitVector &used, bool includeReserved) {
if (includeReserved)
used = RegStates;
else
used = RegStates & ~ReservedRegs;
}
/// CreateRegClassMask - Set the bits that represent the registers in the /// CreateRegClassMask - Set the bits that represent the registers in the
/// TargetRegisterClass. /// TargetRegisterClass.
static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) { static void CreateRegClassMask(const TargetRegisterClass *RC, BitVector &Mask) {