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https://github.com/c64scene-ar/llvm-6502.git
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Add the final MMX instructions. Correct a few wrong patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36405 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
6dd29e08f7
commit
69dc5332de
@ -704,4 +704,8 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
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def int_x86_mmx_pmovmskb : GCCBuiltin<"__builtin_ia32_pmovmskb">,
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Intrinsic<[llvm_i32_ty, llvm_v8i8_ty], [IntrNoMem]>;
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def int_x86_mmx_movnt_dq : GCCBuiltin<"__builtin_ia32_movntq">,
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Intrinsic<[llvm_void_ty, llvm_ptr_ty,
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llvm_v1i64_ty], [IntrWriteMem]>;
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}
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@ -61,14 +61,42 @@ def bc_v1i64 : PatFrag<(ops node:$in), (v1i64 (bitconvert node:$in))>;
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// MMX Masks
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//===----------------------------------------------------------------------===//
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// MMX_SHUFFLE_get_shuf_imm xform function: convert vector_shuffle mask to
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// PSHUFW imm.
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def MMX_SHUFFLE_get_shuf_imm : SDNodeXForm<build_vector, [{
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return getI8Imm(X86::getShuffleSHUFImmediate(N));
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}]>;
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// Patterns for: vector_shuffle v1, v2, <2, 6, 3, 7, ...>
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def MMX_UNPCKH_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKHMask(N);
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}]>;
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// Patterns for: vector_shuffle v1, v2, <0, 4, 2, 5, ...>
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def MMX_UNPCKL_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKLMask(N);
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}]>;
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// Patterns for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
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def MMX_UNPCKH_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKH_v_undef_Mask(N);
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}]>;
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// Patterns for: vector_shuffle v1, <undef>, <2, 2, 3, 3, ...>
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def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKL_v_undef_Mask(N);
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}]>;
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// Patterns for shuffling.
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def MMX_PSHUFW_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isPSHUFDMask(N);
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}], MMX_SHUFFLE_get_shuf_imm>;
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// Patterns for: vector_shuffle v1, v2, <4, 5, 2, 3>; etc.
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def MMX_MOVL_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isMOVLMask(N);
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}]>;
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//===----------------------------------------------------------------------===//
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// MMX Multiclasses
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//===----------------------------------------------------------------------===//
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@ -166,15 +194,35 @@ def MMX_MOVQ64mr : MMXI<0x7F, MRMDestMem, (ops i64mem:$dst, VR64:$src),
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def MMX_MOVDQ2Qrr : MMXID<0xD6, MRMDestMem, (ops VR64:$dst, VR128:$src),
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"movdq2q {$src, $dst|$dst, $src}",
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[(store (i64 (vector_extract (v2i64 VR128:$src),
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(iPTR 0))), VR64:$dst)]>;
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[(set VR64:$dst,
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(v1i64 (vector_extract (v2i64 VR128:$src),
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(iPTR 0))))]>;
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def MMX_MOVQ2DQrr : MMXIS<0xD6, MRMDestMem, (ops VR128:$dst, VR64:$src),
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"movq2dq {$src, $dst|$dst, $src}",
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[(store (v1i64 VR64:$src), VR128:$dst)]>;
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[(set VR128:$dst,
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(bitconvert (v1i64 VR64:$src)))]>;
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def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (ops i64mem:$dst, VR64:$src),
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"movntq {$src, $dst|$dst, $src}", []>;
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"movntq {$src, $dst|$dst, $src}",
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[(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>;
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let AddedComplexity = 15 in
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// movd to MMX register zero-extends
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def MMX_MOVZDI2PDIrr : MMX2I<0x6E, MRMSrcReg, (ops VR64:$dst, GR32:$src),
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"movd {$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(v2i32 (vector_shuffle immAllZerosV,
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(v2i32 (scalar_to_vector GR32:$src)),
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MMX_MOVL_shuffle_mask)))]>;
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let AddedComplexity = 20 in
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def MMX_MOVZDI2PDIrm : MMX2I<0x6E, MRMSrcMem, (ops VR64:$dst, i32mem:$src),
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"movd {$src, $dst|$dst, $src}",
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[(set VR64:$dst,
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(v2i32 (vector_shuffle immAllZerosV,
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(v2i32 (scalar_to_vector
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(loadi32 addr:$src))),
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MMX_MOVL_shuffle_mask)))]>;
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// Arithmetic Instructions
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@ -194,6 +242,7 @@ defm MMX_PADDUSW : MMXI_binop_rm_int<0xDD, "paddusw", int_x86_mmx_paddus_w, 1>;
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defm MMX_PSUBB : MMXI_binop_rm<0xF8, "psubb", sub, v8i8>;
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defm MMX_PSUBW : MMXI_binop_rm<0xF9, "psubw", sub, v4i16>;
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defm MMX_PSUBD : MMXI_binop_rm<0xFA, "psubd", sub, v2i32>;
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defm MMX_PSUBQ : MMXI_binop_rm<0xFB, "psubq", sub, v1i64>;
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defm MMX_PSUBSB : MMXI_binop_rm_int<0xE8, "psubsb" , int_x86_mmx_psubs_b>;
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defm MMX_PSUBSW : MMXI_binop_rm_int<0xE9, "psubsw" , int_x86_mmx_psubs_w>;
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@ -365,6 +414,23 @@ defm MMX_PACKSSWB : MMXI_binop_rm_int<0x63, "packsswb", int_x86_mmx_packsswb>;
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defm MMX_PACKSSDW : MMXI_binop_rm_int<0x6B, "packssdw", int_x86_mmx_packssdw>;
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defm MMX_PACKUSWB : MMXI_binop_rm_int<0x67, "packuswb", int_x86_mmx_packuswb>;
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// -- Shuffle Instructions
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def MMX_PSHUFWri : MMXIi8<0x70, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle
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VR64:$src1, (undef),
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MMX_PSHUFW_shuffle_mask:$src2)))]>;
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def MMX_PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
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(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set VR64:$dst,
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(v4i16 (vector_shuffle
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(bc_v4i16 (load_mmx addr:$src1)),
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(undef),
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MMX_PSHUFW_shuffle_mask:$src2)))]>;
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// -- Conversion Instructions
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def MMX_CVTPD2PIrr : MMX2I<0x2D, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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"cvtpd2pi {$src, $dst|$dst, $src}", []>;
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@ -396,14 +462,6 @@ def MMX_CVTTPS2PIrr : MMXI<0x2C, MRMSrcReg, (ops VR64:$dst, VR128:$src),
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def MMX_CVTTPS2PIrm : MMXI<0x2C, MRMSrcMem, (ops VR64:$dst, f64mem:$src),
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"cvttps2pi {$src, $dst|$dst, $src}", []>;
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// Shuffle and unpack instructions
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def PSHUFWri : MMXIi8<0x70, MRMSrcReg,
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(ops VR64:$dst, VR64:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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def PSHUFWmi : MMXIi8<0x70, MRMSrcMem,
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(ops VR64:$dst, i64mem:$src1, i8imm:$src2),
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"pshufw {$src2, $src1, $dst|$dst, $src1, $src2}", []>;
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// Extract / Insert
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def MMX_X86pextrw : SDNode<"X86ISD::PEXTRW", SDTypeProfile<1, 2, []>, []>;
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def MMX_X86pinsrw : SDNode<"X86ISD::PINSRW", SDTypeProfile<1, 3, []>, []>;
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@ -494,16 +552,27 @@ def : Pat<(v1i64 (bitconvert (v8i8 VR64:$src))), (v1i64 VR64:$src)>;
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def MMX_X86s2vec : SDNode<"X86ISD::S2VEC", SDTypeProfile<1, 1, []>, []>;
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// Scalar to v4i16 / v8i8. The source may be a GR32, but only the lower 8 or
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// 16-bits matter.
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// Move scalar to XMM zero-extended
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// movd to XMM register zero-extends
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let AddedComplexity = 15 in {
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def : Pat<(v8i8 (vector_shuffle immAllZerosV,
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(v8i8 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
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(MMX_MOVZDI2PDIrr GR32:$src)>;
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def : Pat<(v4i16 (vector_shuffle immAllZerosV,
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(v4i16 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
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(MMX_MOVZDI2PDIrr GR32:$src)>;
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def : Pat<(v2i32 (vector_shuffle immAllZerosV,
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(v2i32 (MMX_X86s2vec GR32:$src)), MMX_MOVL_shuffle_mask)),
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(MMX_MOVZDI2PDIrr GR32:$src)>;
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}
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// Scalar to v2i32 / v4i16 / v8i8. The source may be a GR32, but only the lower
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// 8 or 16-bits matter.
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def : Pat<(v8i8 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
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def : Pat<(v4i16 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
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def : Pat<(v2i32 (MMX_X86s2vec GR32:$src)), (MMX_MOVD64rr GR32:$src)>;
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// Recipes for: vector_shuffle v1, <undef>, <0, 0, 1, 1, ...>
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def MMX_UNPCKL_v_undef_shuffle_mask : PatLeaf<(build_vector), [{
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return X86::isUNPCKL_v_undef_Mask(N);
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}]>;
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// Patterns to perform canonical versions of vector shuffling.
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let AddedComplexity = 10 in {
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def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
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MMX_UNPCKL_v_undef_shuffle_mask)),
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@ -516,6 +585,19 @@ let AddedComplexity = 10 in {
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(MMX_PUNPCKLDQrr VR64:$src, VR64:$src)>;
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}
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let AddedComplexity = 10 in {
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def : Pat<(v8i8 (vector_shuffle VR64:$src, (undef),
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MMX_UNPCKH_v_undef_shuffle_mask)),
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(MMX_PUNPCKHBWrr VR64:$src, VR64:$src)>;
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def : Pat<(v4i16 (vector_shuffle VR64:$src, (undef),
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MMX_UNPCKH_v_undef_shuffle_mask)),
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(MMX_PUNPCKHWDrr VR64:$src, VR64:$src)>;
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def : Pat<(v2i32 (vector_shuffle VR64:$src, (undef),
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MMX_UNPCKH_v_undef_shuffle_mask)),
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(MMX_PUNPCKHDQrr VR64:$src, VR64:$src)>;
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}
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// Patterns to perform vector shuffling with a zeroed out vector.
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let AddedComplexity = 20 in {
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def : Pat<(bc_v2i32 (vector_shuffle immAllZerosV,
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(v2i32 (scalar_to_vector (load_mmx addr:$src))),
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