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[X86] Factor out the CMOV pseudo definitions. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229206 91177308-0d34-0410-b5e6-96231b3b80d8
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Ahmed Bougacha
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821ec14add
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6a50342499
@ -475,59 +475,50 @@ def TLSCall_64 : I<0, Pseudo, (outs), (ins i64mem:$sym),
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//===----------------------------------------------------------------------===//
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// Conditional Move Pseudo Instructions
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// X86 doesn't have 8-bit conditional moves. Use a customInserter to
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// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
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// however that requires promoting the operands, and can induce additional
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// i8 register pressure.
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// CMOV* - Used to implement the SELECT DAG operation. Expanded after
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// instruction selection into a branch sequence.
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multiclass CMOVrr_PSEUDO<RegisterClass RC, ValueType VT> {
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def CMOV#NAME : I<0, Pseudo,
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(outs RC:$dst), (ins RC:$t, RC:$f, i8imm:$cond),
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"#CMOV_"#NAME#" PSEUDO!",
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[(set RC:$dst, (VT (X86cmov RC:$t, RC:$f, imm:$cond,
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EFLAGS)))]>;
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}
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let usesCustomInserter = 1, Uses = [EFLAGS] in {
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def CMOV_GR8 : I<0, Pseudo,
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(outs GR8:$dst), (ins GR8:$src1, GR8:$src2, i8imm:$cond),
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"#CMOV_GR8 PSEUDO!",
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[(set GR8:$dst, (X86cmov GR8:$src1, GR8:$src2,
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imm:$cond, EFLAGS))]>;
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// X86 doesn't have 8-bit conditional moves. Use a customInserter to
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// emit control flow. An alternative to this is to mark i8 SELECT as Promote,
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// however that requires promoting the operands, and can induce additional
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// i8 register pressure.
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defm _GR8 : CMOVrr_PSEUDO<GR8, i8>;
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let Predicates = [NoCMov] in {
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def CMOV_GR32 : I<0, Pseudo,
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(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cond),
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"#CMOV_GR32* PSEUDO!",
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[(set GR32:$dst,
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(X86cmov GR32:$src1, GR32:$src2, imm:$cond, EFLAGS))]>;
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def CMOV_GR16 : I<0, Pseudo,
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(outs GR16:$dst), (ins GR16:$src1, GR16:$src2, i8imm:$cond),
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"#CMOV_GR16* PSEUDO!",
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[(set GR16:$dst,
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(X86cmov GR16:$src1, GR16:$src2, imm:$cond, EFLAGS))]>;
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} // Predicates = [NoCMov]
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let Predicates = [NoCMov] in {
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defm _GR32 : CMOVrr_PSEUDO<GR32, i32>;
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defm _GR16 : CMOVrr_PSEUDO<GR16, i16>;
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} // Predicates = [NoCMov]
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// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
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// SSE1.
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let Predicates = [FPStackf32] in
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def CMOV_RFP32 : I<0, Pseudo,
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(outs RFP32:$dst),
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(ins RFP32:$src1, RFP32:$src2, i8imm:$cond),
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"#CMOV_RFP32 PSEUDO!",
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[(set RFP32:$dst,
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(X86cmov RFP32:$src1, RFP32:$src2, imm:$cond,
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EFLAGS))]>;
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// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
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// SSE2.
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let Predicates = [FPStackf64] in
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def CMOV_RFP64 : I<0, Pseudo,
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(outs RFP64:$dst),
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(ins RFP64:$src1, RFP64:$src2, i8imm:$cond),
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"#CMOV_RFP64 PSEUDO!",
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[(set RFP64:$dst,
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(X86cmov RFP64:$src1, RFP64:$src2, imm:$cond,
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EFLAGS))]>;
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def CMOV_RFP80 : I<0, Pseudo,
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(outs RFP80:$dst),
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(ins RFP80:$src1, RFP80:$src2, i8imm:$cond),
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"#CMOV_RFP80 PSEUDO!",
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[(set RFP80:$dst,
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(X86cmov RFP80:$src1, RFP80:$src2, imm:$cond,
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EFLAGS))]>;
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} // UsesCustomInserter = 1, Uses = [EFLAGS]
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// fcmov doesn't handle all possible EFLAGS, provide a fallback if there is no
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// SSE1/SSE2.
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let Predicates = [FPStackf32] in
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defm _RFP32 : CMOVrr_PSEUDO<RFP32, f32>;
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let Predicates = [FPStackf64] in
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defm _RFP64 : CMOVrr_PSEUDO<RFP64, f64>;
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defm _RFP80 : CMOVrr_PSEUDO<RFP80, f80>;
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defm _FR32 : CMOVrr_PSEUDO<FR32, f32>;
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defm _FR64 : CMOVrr_PSEUDO<FR64, f64>;
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defm _V4F32 : CMOVrr_PSEUDO<VR128, v4f32>;
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defm _V2F64 : CMOVrr_PSEUDO<VR128, v2f64>;
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defm _V2I64 : CMOVrr_PSEUDO<VR128, v2i64>;
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defm _V8F32 : CMOVrr_PSEUDO<VR256, v8f32>;
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defm _V4F64 : CMOVrr_PSEUDO<VR256, v4f64>;
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defm _V4I64 : CMOVrr_PSEUDO<VR256, v4i64>;
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defm _V8I64 : CMOVrr_PSEUDO<VR512, v8i64>;
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defm _V8F64 : CMOVrr_PSEUDO<VR512, v8f64>;
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defm _V16F32 : CMOVrr_PSEUDO<VR512, v16f32>;
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} // usesCustomInserter = 1, Uses = [EFLAGS]
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//===----------------------------------------------------------------------===//
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// Normal-Instructions-With-Lock-Prefix Pseudo Instructions
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@ -863,79 +854,6 @@ def ACQUIRE_MOV32rm : I<0, Pseudo, (outs GR32:$dst), (ins i32mem:$src),
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def ACQUIRE_MOV64rm : I<0, Pseudo, (outs GR64:$dst), (ins i64mem:$src),
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"#ACQUIRE_MOV PSEUDO!",
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[(set GR64:$dst, (atomic_load_64 addr:$src))]>;
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//===----------------------------------------------------------------------===//
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// Conditional Move Pseudo Instructions.
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//===----------------------------------------------------------------------===//
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// CMOV* - Used to implement the SSE SELECT DAG operation. Expanded after
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// instruction selection into a branch sequence.
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let Uses = [EFLAGS], usesCustomInserter = 1 in {
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def CMOV_FR32 : I<0, Pseudo,
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(outs FR32:$dst), (ins FR32:$t, FR32:$f, i8imm:$cond),
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"#CMOV_FR32 PSEUDO!",
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[(set FR32:$dst, (X86cmov FR32:$t, FR32:$f, imm:$cond,
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EFLAGS))]>;
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def CMOV_FR64 : I<0, Pseudo,
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(outs FR64:$dst), (ins FR64:$t, FR64:$f, i8imm:$cond),
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"#CMOV_FR64 PSEUDO!",
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[(set FR64:$dst, (X86cmov FR64:$t, FR64:$f, imm:$cond,
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EFLAGS))]>;
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def CMOV_V4F32 : I<0, Pseudo,
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(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
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"#CMOV_V4F32 PSEUDO!",
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[(set VR128:$dst,
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(v4f32 (X86cmov VR128:$t, VR128:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V2F64 : I<0, Pseudo,
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(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
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"#CMOV_V2F64 PSEUDO!",
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[(set VR128:$dst,
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(v2f64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V2I64 : I<0, Pseudo,
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(outs VR128:$dst), (ins VR128:$t, VR128:$f, i8imm:$cond),
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"#CMOV_V2I64 PSEUDO!",
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[(set VR128:$dst,
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(v2i64 (X86cmov VR128:$t, VR128:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V8F32 : I<0, Pseudo,
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(outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
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"#CMOV_V8F32 PSEUDO!",
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[(set VR256:$dst,
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(v8f32 (X86cmov VR256:$t, VR256:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V4F64 : I<0, Pseudo,
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(outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
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"#CMOV_V4F64 PSEUDO!",
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[(set VR256:$dst,
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(v4f64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V4I64 : I<0, Pseudo,
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(outs VR256:$dst), (ins VR256:$t, VR256:$f, i8imm:$cond),
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"#CMOV_V4I64 PSEUDO!",
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[(set VR256:$dst,
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(v4i64 (X86cmov VR256:$t, VR256:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V8I64 : I<0, Pseudo,
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(outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
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"#CMOV_V8I64 PSEUDO!",
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[(set VR512:$dst,
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(v8i64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V8F64 : I<0, Pseudo,
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(outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
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"#CMOV_V8F64 PSEUDO!",
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[(set VR512:$dst,
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(v8f64 (X86cmov VR512:$t, VR512:$f, imm:$cond,
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EFLAGS)))]>;
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def CMOV_V16F32 : I<0, Pseudo,
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(outs VR512:$dst), (ins VR512:$t, VR512:$f, i8imm:$cond),
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"#CMOV_V16F32 PSEUDO!",
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[(set VR512:$dst,
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(v16f32 (X86cmov VR512:$t, VR512:$f, imm:$cond,
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EFLAGS)))]>;
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}
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//===----------------------------------------------------------------------===//
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// DAG Pattern Matching Rules
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