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https://github.com/c64scene-ar/llvm-6502.git
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Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls
clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity, instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when the code is actually located above the 4G boundary. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31734 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner
parent
d10434215d
commit
6a5339ba65
@ -102,6 +102,7 @@ void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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case PPC::IMPLICIT_DEF_VRRC:
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break; // pseudo opcode, no side effects
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case PPC::MovePCtoLR:
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case PPC::MovePCtoLR8:
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assert(0 && "CodeEmitter does not support MovePCtoLR instruction");
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break;
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}
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@ -60,11 +60,52 @@ def HI48_64 : SDNodeXForm<imm, [{
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def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD",
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[(set G8RC:$rD, (undef))]>;
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//===----------------------------------------------------------------------===//
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// Calls.
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//
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let Defs = [LR8] in
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def MovePCtoLR8 : Pseudo<(ops piclabel:$label), "bl $label", []>,
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PPC970_Unit_BRU;
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let isCall = 1, noResults = 1, PPC970_Unit = 7,
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// All calls clobber the PPC64 non-callee saved registers.
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Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
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F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
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V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
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LR8,CTR8,
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CR0,CR1,CR5,CR6,CR7] in {
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// Convenient aliases for call instructions
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def BL8 : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
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"bl $func", BrB, []>; // See Pat patterns below.
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def BLA8 : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
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"bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
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}
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// Calls
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def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
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(BL8 tglobaladdr:$dst)>;
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def : Pat<(PPCcall (i64 texternalsym:$dst)),
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(BL8 texternalsym:$dst)>;
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//===----------------------------------------------------------------------===//
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// 64-bit SPR manipulation instrs.
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def MFCTR8 : XFXForm_1_ext<31, 339, 9, (ops G8RC:$rT), "mfctr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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let Pattern = [(PPCmtctr G8RC:$rS)] in {
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def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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PPC970_DGroup_First, PPC970_Unit_FXU;
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}
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def MTLR8 : XFXForm_7_ext<31, 467, 8, (ops G8RC:$rS), "mtlr $rS", SprMTSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>,
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PPC970_DGroup_First, PPC970_Unit_FXU;
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//===----------------------------------------------------------------------===//
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// Fixed point instructions.
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//
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@ -274,6 +274,7 @@ def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
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// PowerPC Instruction Predicate Definitions.
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def FPContractions : Predicate<"!NoExcessFPPrecision">;
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//===----------------------------------------------------------------------===//
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// PowerPC Instruction Definitions.
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@ -328,6 +329,7 @@ let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
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}
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let Defs = [LR] in
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def MovePCtoLR : Pseudo<(ops piclabel:$label), "bl $label", []>,
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PPC970_Unit_BRU;
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@ -1014,9 +1016,9 @@ def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
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(RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
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// Calls
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def : Pat<(PPCcall tglobaladdr:$dst),
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def : Pat<(PPCcall (i32 tglobaladdr:$dst)),
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(BL tglobaladdr:$dst)>;
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def : Pat<(PPCcall texternalsym:$dst),
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def : Pat<(PPCcall (i32 texternalsym:$dst)),
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(BL texternalsym:$dst)>;
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// Hi and Lo for Darwin Global Addresses.
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@ -99,12 +99,32 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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if (SrcReg == PPC::LR) {
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// FIXME: this spills LR immediately to memory in one step. To do this, we
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// use R11, which we know cannot be used in the prolog/epilog. This is a
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// hack.
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BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
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if (RC == PPC::GPRCRegisterClass) {
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if (SrcReg != PPC::LR) {
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
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} else {
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// FIXME: this spills LR immediately to memory in one step. To do this,
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// we use R11, which we know cannot be used in the prolog/epilog. This is
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// a hack.
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BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11),
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FrameIdx);
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}
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} else if (RC == PPC::G8RCRegisterClass) {
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if (SrcReg != PPC::LR8) {
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addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg), FrameIdx);
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} else {
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// FIXME: this spills LR immediately to memory in one step. To do this,
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// we use R11, which we know cannot be used in the prolog/epilog. This is
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// a hack.
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BuildMI(MBB, MI, PPC::MFLR8, 1, PPC::X11);
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addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(PPC::X11),
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FrameIdx);
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}
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} else if (RC == PPC::F8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::CRRCRegisterClass) {
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// FIXME: We use R0 here, because it isn't available for RA.
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// We need to store the CR in the low 4-bits of the saved value. First,
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@ -121,14 +141,6 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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}
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R0), FrameIdx);
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} else if (RC == PPC::GPRCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::G8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STD, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::F8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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@ -146,12 +158,27 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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void
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PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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if (DestReg == PPC::LR) {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
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BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
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MachineBasicBlock::iterator MI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const {
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if (RC == PPC::GPRCRegisterClass) {
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if (DestReg != PPC::LR) {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
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} else {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R11), FrameIdx);
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BuildMI(MBB, MI, PPC::MTLR, 1).addReg(PPC::R11);
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}
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} else if (RC == PPC::G8RCRegisterClass) {
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if (DestReg != PPC::LR8) {
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addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
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} else {
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addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, PPC::R11), FrameIdx);
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BuildMI(MBB, MI, PPC::MTLR8, 1).addReg(PPC::R11);
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}
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} else if (RC == PPC::F8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
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} else if (RC == PPC::CRRCRegisterClass) {
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// FIXME: We use R0 here, because it isn't available for RA.
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, PPC::R0), FrameIdx);
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@ -166,14 +193,6 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
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}
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BuildMI(MBB, MI, PPC::MTCRF, 1, DestReg).addReg(PPC::R0);
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} else if (RC == PPC::GPRCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LWZ, 2, DestReg), FrameIdx);
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} else if (RC == PPC::G8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LD, 2, DestReg), FrameIdx);
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} else if (RC == PPC::F8RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
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} else if (RC == PPC::F4RCRegisterClass) {
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addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
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} else if (RC == PPC::VRRCRegisterClass) {
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// We don't have indexed addressing for vector loads. Emit:
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// R11 = ADDI FI#
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@ -251,7 +270,7 @@ const unsigned* PPCRegisterInfo::getCalleeSaveRegs() const {
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PPC::V24, PPC::V25, PPC::V26, PPC::V27,
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PPC::V28, PPC::V29, PPC::V30, PPC::V31,
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PPC::LR, 0
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PPC::LR8, 0
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};
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return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegs :
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@ -303,7 +322,7 @@ PPCRegisterInfo::getCalleeSaveRegClasses() const {
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&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
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&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,&PPC::VRRCRegClass,
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&PPC::GPRCRegClass, 0
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&PPC::G8RCRegClass, 0
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};
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return Subtarget.isPPC64() ? Darwin64_CalleeSaveRegClasses :
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@ -780,7 +799,8 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
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}
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unsigned PPCRegisterInfo::getRARegister() const {
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return PPC::LR;
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return !Subtarget.isPPC64() ? PPC::LR : PPC::LR8;
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}
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unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
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@ -195,8 +195,13 @@ def CR7 : CR<7, "cr7">, DwarfRegNum<75>;
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// Link register
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def LR : SPR<8, "lr">, DwarfRegNum<65>;
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//let Aliases = [LR] in
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def LR8 : SPR<8, "lr">, DwarfRegNum<65>;
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// Count register
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def CTR : SPR<9, "ctr">, DwarfRegNum<66>;
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def CTR : SPR<9, "ctr">, DwarfRegNum<66>;
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def CTR8 : SPR<9, "ctr">, DwarfRegNum<66>;
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// VRsave register
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def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>;
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@ -229,7 +234,7 @@ def GPRC : RegisterClass<"PPC", [i32], 32,
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def G8RC : RegisterClass<"PPC", [i64], 64,
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[X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12,
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X30, X29, X28, X27, X26, X25, X24, X23, X22, X21, X20, X19, X18, X17,
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X16, X15, X14, X13, X31, X0, X1]>
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X16, X15, X14, X13, X31, X0, X1, LR8]>
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{
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let MethodProtos = [{
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iterator allocation_order_begin(const MachineFunction &MF) const;
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@ -243,9 +248,9 @@ def G8RC : RegisterClass<"PPC", [i64], 64,
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G8RCClass::iterator
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G8RCClass::allocation_order_end(const MachineFunction &MF) const {
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if (hasFP(MF))
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return end()-3;
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return end()-4;
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else
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return end()-2;
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return end()-3;
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}
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}];
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}
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