6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-01-10 02:36:06 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Relax a few tests to help enable scheduler

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@217320 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault 2014-09-06 20:44:41 +00:00
parent 360ed46f68
commit 6a712e709d
6 changed files with 25 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
test/CodeGen/R600/array-ptr-calc-i32.ll
View File

@ -22,8 +22,8 @@ declare void @llvm.AMDGPU.barrier.local() nounwind noduplicate
; to interpret:
; getelementptr [4 x i32]* %alloca, i32 1, i32 %b
; SI-PROMOTE: V_ADD_I32_e32 [[PTRREG:v[0-9]+]]
; SI-PROMOTE: DS_WRITE_B32 {{v[0-9]+}}, [[PTRREG]]
; SI-PROMOTE: V_ADD_I32_e32 [[PTRREG:v[0-9]+]], 16
; SI-PROMOTE: DS_WRITE_B32 [[PTRREG]]
define void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) {
%alloca = alloca [4 x i32], i32 4, align 16
%tid = call i32 @llvm.SI.tid() readnone

4
test/CodeGen/R600/fceil64.ll
View File

@ -15,8 +15,8 @@ declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
; SI: S_LSHR_B64
; SI: S_NOT_B64
; SI: S_AND_B64
; SI: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
; SI: CMP_LT_I32
; SI-DAG: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
; SI-DAG: CMP_LT_I32
; SI: CNDMASK_B32
; SI: CNDMASK_B32
; SI: CMP_GT_I32

2
test/CodeGen/R600/fcopysign.f32.ll
View File

@ -10,7 +10,7 @@ declare <4 x float> @llvm.copysign.v4f32(<4 x float>, <4 x float>) nounwind read
; FUNC-LABEL: @test_copysign_f32:
; SI: S_LOAD_DWORD [[SMAG:s[0-9]+]], {{.*}} 0xb
; SI: S_LOAD_DWORD [[SSIGN:s[0-9]+]], {{.*}} 0xc
; SI: V_MOV_B32_e32 [[VSIGN:v[0-9]+]], [[SSIGN]]
; SI-DAG: V_MOV_B32_e32 [[VSIGN:v[0-9]+]], [[SSIGN]]
; SI-DAG: V_MOV_B32_e32 [[VMAG:v[0-9]+]], [[SMAG]]
; SI-DAG: S_MOV_B32 [[SCONST:s[0-9]+]], 0x7fffffff
; SI: V_BFI_B32 [[RESULT:v[0-9]+]], [[SCONST]], [[VMAG]], [[VSIGN]]

4
test/CodeGen/R600/ffloor.ll
View File

@ -16,8 +16,8 @@ declare <16 x double> @llvm.floor.v16f64(<16 x double>) nounwind readnone
; SI: S_LSHR_B64
; SI: S_NOT_B64
; SI: S_AND_B64
; SI: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
; SI: CMP_LT_I32
; SI-DAG: S_AND_B32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
; SI-DAG: CMP_LT_I32
; SI: CNDMASK_B32
; SI: CNDMASK_B32
; SI: CMP_GT_I32

34
test/CodeGen/R600/llvm.SI.resinfo.ll
View File

@ -1,21 +1,21 @@
;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s
; RUN: llc -march=r600 -mcpu=verde -verify-machineinstrs < %s | FileCheck %s
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 2, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 1, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 4, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 8, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 9, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 6, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 10, 0, 0, -1
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 11, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 13, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 14, 0, 0, 0
;CHECK: IMAGE_GET_RESINFO {{v[0-9]+}}, 8, 0, 0, -1
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 15, 0, 0, -1
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 3, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 2, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 1, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 4, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 8, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 5, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 9, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 6, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 10, 0, 0, -1
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 12, 0, 0, -1
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 7, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 11, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 13, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v\[[0-9]+:[0-9]+\]}}, 14, 0, 0, 0
; CHECK-DAG: IMAGE_GET_RESINFO {{v[0-9]+}}, 8, 0, 0, -1
define void @test(i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8,
i32 %a9, i32 %a10, i32 %a11, i32 %a12, i32 %a13, i32 %a14, i32 %a15, i32 %a16) {

2
test/CodeGen/R600/rotr.i64.ll
View File

@ -3,7 +3,7 @@
; FUNC-LABEL: @s_rotr_i64
; SI-DAG: S_SUB_I32
; SI-DAG: S_LSHR_B64
; SI: S_LSHL_B64
; SI-DAG: S_LSHL_B64
; SI: S_OR_B64
define void @s_rotr_i64(i64 addrspace(1)* %in, i64 %x, i64 %y) {
entry: