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[X86] Improved lowering of packed vector shifts to vpsllq/vpsrlq.

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SSE2/AVX non-constant packed shift instructions only use the lower 64-bit of
the shift count. 

This patch teaches function 'getTargetVShiftNode' how to deal with shifts
where the shift count node is of type MVT::i64.

Before this patch, function 'getTargetVShiftNode' only knew how to deal with
shift count nodes of type MVT::i32. This forced the backend to wrongly
truncate the shift count to MVT::i32, and then zero-extend it back to MVT::i64.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
2014-12-05 20:02:22 +00:00
parent 189606dbfe
commit 6a9a49d7ab
2 changed files with 17 additions and 18 deletions
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8
test/CodeGen/X86/lower-vec-shift-2.ll
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@@ -44,14 +44,10 @@ entry:
define <2 x i64> @test3(<2 x i64> %A, <2 x i64> %B) {
; SSE2-LABEL: test3:
; SSE2: # BB#0
; SSE2-NEXT: movd %xmm1, %rax
; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psllq %xmm1, %xmm0
; SSE2-NEXT: retq
; AVX-LABEL: test3:
; AVX: # BB#0
; AVX-NEXT: vmovq %xmm1, %rax
; AVX-NEXT: vmovd %eax, %xmm1
; AVX-NEXT: vpsllq %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
entry:
@@ -103,14 +99,10 @@ entry:
define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) {
; SSE2-LABEL: test6:
; SSE2: # BB#0
; SSE2-NEXT: movd %xmm1, %rax
; SSE2-NEXT: movd %eax, %xmm1
; SSE2-NEXT: psrlq %xmm1, %xmm0
; SSE2-NEXT: retq
; AVX-LABEL: test6:
; AVX: # BB#0
; AVX-NEXT: vmovq %xmm1, %rax
; AVX-NEXT: vmovd %eax, %xmm1
; AVX-NEXT: vpsrlq %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
entry: