mirror of
https://github.com/c64scene-ar/llvm-6502.git
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[Stackmap] Emit multi-byte nops for X86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196334 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka
parent
4f47f014cd
commit
6abfcbdfc8
@ -674,27 +674,76 @@ static void LowerTlsAddr(MCStreamer &OutStreamer,
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.addExpr(tlsRef));
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}
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/// \brief Emit the optimal amount of multi-byte nops on X86.
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static void EmitNops(MCStreamer &OS, unsigned NumBytes, bool Is64Bit) {
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// This works only for 64bit. For 32bit we have to do additional checking if
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// the CPU supports multi-byte nops.
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assert(Is64Bit && "EmitNops only supports X86-64");
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while (NumBytes) {
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unsigned Opc, BaseReg, ScaleVal, IndexReg, Displacement, SegmentReg;
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Opc = IndexReg = Displacement = SegmentReg = 0;
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BaseReg = X86::RAX; ScaleVal = 1;
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switch (NumBytes) {
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case 0: llvm_unreachable("Zero nops?"); break;
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case 1: NumBytes -= 1; Opc = X86::NOOP; break;
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case 2: NumBytes -= 2; Opc = X86::XCHG16ar; break;
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case 3: NumBytes -= 3; Opc = X86::NOOPL; break;
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case 4: NumBytes -= 4; Opc = X86::NOOPL; Displacement = 8; break;
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case 5: NumBytes -= 5; Opc = X86::NOOPL; Displacement = 8;
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IndexReg = X86::RAX; break;
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case 6: NumBytes -= 6; Opc = X86::NOOPW; Displacement = 8;
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IndexReg = X86::RAX; break;
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case 7: NumBytes -= 7; Opc = X86::NOOPL; Displacement = 512; break;
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case 8: NumBytes -= 8; Opc = X86::NOOPL; Displacement = 512;
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IndexReg = X86::RAX; break;
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case 9: NumBytes -= 9; Opc = X86::NOOPW; Displacement = 512;
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IndexReg = X86::RAX; break;
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default: NumBytes -= 10; Opc = X86::NOOPW; Displacement = 512;
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IndexReg = X86::RAX; SegmentReg = X86::CS; break;
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}
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unsigned NumPrefixes = std::min(NumBytes, 5U);
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NumBytes -= NumPrefixes;
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for (unsigned i = 0; i != NumPrefixes; ++i)
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OS.EmitBytes("\x66");
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switch (Opc) {
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default: llvm_unreachable("Unexpected opcode"); break;
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case X86::NOOP:
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OS.EmitInstruction(MCInstBuilder(Opc));
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break;
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case X86::XCHG16ar:
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OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX));
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break;
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case X86::NOOPL:
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case X86::NOOPW:
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OS.EmitInstruction(MCInstBuilder(Opc).addReg(BaseReg).addImm(ScaleVal)
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.addReg(IndexReg)
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.addImm(Displacement)
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.addReg(SegmentReg));
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break;
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}
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} // while (NumBytes)
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}
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// Lower a stackmap of the form:
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// <id>, <shadowBytes>, ...
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static void LowerSTACKMAP(MCStreamer &OutStreamer,
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StackMaps &SM,
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const MachineInstr &MI)
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{
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unsigned NumNOPBytes = MI.getOperand(1).getImm();
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static void LowerSTACKMAP(MCStreamer &OS, StackMaps &SM,
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const MachineInstr &MI, bool Is64Bit) {
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unsigned NumBytes = MI.getOperand(1).getImm();
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SM.recordStackMap(MI);
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// Emit padding.
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// FIXME: These nops ensure that the stackmap's shadow is covered by
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// instructions from the same basic block, but the nops should not be
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// necessary if instructions from the same block follow the stackmap.
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for (unsigned i = 0; i < NumNOPBytes; ++i)
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OutStreamer.EmitInstruction(MCInstBuilder(X86::NOOP));
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EmitNops(OS, NumBytes, Is64Bit);
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}
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// Lower a patchpoint of the form:
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// [<def>], <id>, <numBytes>, <target>, <numArgs>, <cc>, ...
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static void LowerPATCHPOINT(MCStreamer &OutStreamer,
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StackMaps &SM,
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const MachineInstr &MI) {
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static void LowerPATCHPOINT(MCStreamer &OS, StackMaps &SM,
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const MachineInstr &MI, bool Is64Bit) {
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assert(Is64Bit && "Patchpoint currently only supports X86-64");
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SM.recordPatchPoint(MI);
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PatchPointOpers opers(&MI);
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@ -704,22 +753,21 @@ static void LowerPATCHPOINT(MCStreamer &OutStreamer,
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if (CallTarget) {
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// Emit MOV to materialize the target address and the CALL to target.
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// This is encoded with 12-13 bytes, depending on which register is used.
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// We conservatively assume that it is 12 bytes and emit in worst case one
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// extra NOP byte.
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EncodedBytes = 12;
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OutStreamer.EmitInstruction(MCInstBuilder(X86::MOV64ri)
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.addReg(MI.getOperand(ScratchIdx).getReg())
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.addImm(CallTarget));
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OutStreamer.EmitInstruction(MCInstBuilder(X86::CALL64r)
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.addReg(MI.getOperand(ScratchIdx).getReg()));
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unsigned ScratchReg = MI.getOperand(ScratchIdx).getReg();
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if (X86II::isX86_64ExtendedReg(ScratchReg))
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EncodedBytes = 13;
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else
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EncodedBytes = 12;
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OS.EmitInstruction(MCInstBuilder(X86::MOV64ri).addReg(ScratchReg)
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.addImm(CallTarget));
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OS.EmitInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg));
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}
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// Emit padding.
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unsigned NumBytes = opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
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assert(NumBytes >= EncodedBytes &&
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"Patchpoint can't request size less than the length of a call.");
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for (unsigned i = EncodedBytes; i < NumBytes; ++i)
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OutStreamer.EmitInstruction(MCInstBuilder(X86::NOOP));
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EmitNops(OS, NumBytes - EncodedBytes, Is64Bit);
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}
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void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
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@ -813,10 +861,10 @@ void X86AsmPrinter::EmitInstruction(const MachineInstr *MI) {
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}
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case TargetOpcode::STACKMAP:
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return LowerSTACKMAP(OutStreamer, SM, *MI);
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return LowerSTACKMAP(OutStreamer, SM, *MI, Subtarget->is64Bit());
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case TargetOpcode::PATCHPOINT:
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return LowerPATCHPOINT(OutStreamer, SM, *MI);
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return LowerPATCHPOINT(OutStreamer, SM, *MI, Subtarget->is64Bit());
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case X86::MORESTACK_RET:
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OutStreamer.EmitInstruction(MCInstBuilder(X86::RET));
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@ -7,10 +7,10 @@ entry:
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; CHECK-LABEL: trivial_patchpoint_codegen:
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; CHECK: movabsq $-559038736, %r11
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; CHECK-NEXT: callq *%r11
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; CHECK-NEXT: nop
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; CHECK-NEXT: xchgw %ax, %ax
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; CHECK: movq %rax, %[[REG:r.+]]
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; CHECK: callq *%r11
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; CHECK-NEXT: nop
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; CHECK-NEXT: xchgw %ax, %ax
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; CHECK: movq %[[REG]], %rax
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; CHECK: ret
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%resolveCall2 = inttoptr i64 -559038736 to i8*
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@ -84,11 +84,7 @@ define void @small_patchpoint_codegen(i64 %p1, i64 %p2, i64 %p3, i64 %p4) {
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entry:
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; CHECK-LABEL: small_patchpoint_codegen:
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; CHECK: Ltmp
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; CHECK: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK-NEXT: nop
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; CHECK: nopl 8(%rax,%rax)
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; CHECK-NEXT: popq
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; CHECK-NEXT: ret
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%result = tail call i64 (i32, i32, i8*, i32, ...)* @llvm.experimental.patchpoint.i64(i32 5, i32 5, i8* null, i32 2, i64 %p1, i64 %p2)
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230
test/CodeGen/X86/stackmap-nops.ll
Normal file
230
test/CodeGen/X86/stackmap-nops.ll
Normal file
@ -0,0 +1,230 @@
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim | FileCheck %s
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define void @nop_test() {
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entry:
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; CHECK-LABEL: nop_test:
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; CHECK: nop
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; CHECK: xchgw %ax, %ax
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; CHECK: nopl (%rax)
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; CHECK: nopl 8(%rax)
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; CHECK: nopl 8(%rax,%rax)
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; CHECK: nopw 8(%rax,%rax)
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; CHECK: nopl 512(%rax)
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; CHECK: nopl 512(%rax,%rax)
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; CHECK: nopw 512(%rax,%rax)
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; CHECK: nopw %cs:512(%rax,%rax)
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; 11
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; CHECK: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; 12
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; 13
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; 14
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; 15
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; 16
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: nop
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; 17
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: xchgw %ax, %ax
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; 18
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: nopl (%rax)
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; 19
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: nopl 8(%rax)
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; 20
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: nopl 8(%rax,%rax)
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; 21
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: nopw 8(%rax,%rax)
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; 22
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: nopl 512(%rax)
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; 23
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: nopl 512(%rax,%rax)
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; 24
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: nopw 512(%rax,%rax)
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; 25
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; 26
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; 27
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; 28
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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;29
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; 30
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; CHECK: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: .byte 102
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; CHECK-NEXT: nopw %cs:512(%rax,%rax)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 0, i32 0)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 1, i32 1)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 2, i32 2)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 3, i32 3)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 4, i32 4)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 5, i32 5)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 6, i32 6)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 7, i32 7)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 8, i32 8)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 9, i32 9)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 10, i32 10)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 11, i32 11)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 12, i32 12)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 13, i32 13)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 14, i32 14)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 15, i32 15)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 16, i32 16)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 17, i32 17)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 18, i32 18)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 19, i32 19)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 20, i32 20)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 21, i32 21)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 22, i32 22)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 23, i32 23)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 24, i32 24)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 25, i32 25)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 26, i32 26)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 27, i32 27)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 28, i32 28)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 29, i32 29)
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tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 30, i32 30)
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ret void
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}
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declare void @llvm.experimental.stackmap(i32, i32, ...)
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47
test/MC/X86/stackmap-nops.ll
Normal file
47
test/MC/X86/stackmap-nops.ll
Normal file
@ -0,0 +1,47 @@
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; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim -filetype=obj %s -o - | llvm-objdump -d - | FileCheck %s
|
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; RUN: llc -mtriple=x86_64-apple-darwin -mcpu=corei7 -disable-fp-elim -filetype=asm %s -o - | llvm-mc -filetype=obj - | llvm-objdump -d - | FileCheck %s
|
||||
|
||||
define void @nop_test() {
|
||||
entry:
|
||||
; CHECK: 0: 55
|
||||
; CHECK: 1: 48 89 e5
|
||||
|
||||
; CHECK: 4: 90
|
||||
; CHECK: 5: 66 90
|
||||
; CHECK: 7: 0f 1f 00
|
||||
; CHECK: a: 0f 1f 40 08
|
||||
; CHECK: e: 0f 1f 44 00 08
|
||||
; CHECK: 13: 66 0f 1f 44 00 08
|
||||
; CHECK: 19: 0f 1f 80 00 02 00 00
|
||||
; CHECK: 20: 0f 1f 84 00 00 02 00 00
|
||||
; CHECK: 28: 66 0f 1f 84 00 00 02 00 00
|
||||
; CHECK: 31: 2e 66 0f 1f 84 00 00 02 00 00
|
||||
; CHECK: 3b: 66 2e 66 0f 1f 84 00 00 02 00 00
|
||||
; CHECK: 46: 66 66 2e 66 0f 1f 84 00 00 02 00 00
|
||||
; CHECK: 52: 66 66 66 2e 66 0f 1f 84 00 00 02 00 00
|
||||
; CHECK: 5f: 66 66 66 66 2e 66 0f 1f 84 00 00 02 00 00
|
||||
; CHECK: 6d: 66 66 66 66 66 2e 66 0f 1f 84 00 00 02 00 00
|
||||
|
||||
; CHECK: 7c: 5d
|
||||
; CHECK: 7d: c3
|
||||
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 0, i32 0)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 1, i32 1)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 2, i32 2)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 3, i32 3)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 4, i32 4)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 5, i32 5)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 6, i32 6)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 7, i32 7)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 8, i32 8)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 9, i32 9)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 10, i32 10)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 11, i32 11)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 12, i32 12)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 13, i32 13)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 14, i32 14)
|
||||
tail call void (i32, i32, ...)* @llvm.experimental.stackmap(i32 15, i32 15)
|
||||
ret void
|
||||
}
|
||||
|
||||
declare void @llvm.experimental.stackmap(i32, i32, ...)
|
||||
Loading…
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Reference in New Issue
Block a user