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Rename ComputeMaskedBits to computeKnownBits. "Masked" has been

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inappropriate since it lost its Mask parameter in r154011.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208811 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jay Foad 2014-05-14 21:14:37 +00:00
parent cd237ed585
commit 6b543713a2
44 changed files with 311 additions and 313 deletions
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11
include/llvm/Analysis/ValueTracking.h
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@ -27,21 +27,20 @@ namespace llvm {
class MDNode; class MDNode;
class TargetLibraryInfo; class TargetLibraryInfo;
/// ComputeMaskedBits - Determine which bits of V are /// Determine which bits of V are known to be either zero or one and return
/// known to be either zero or one and return them in the KnownZero/KnownOne /// them in the KnownZero/KnownOne bit sets.
/// bit sets.
/// ///
/// This function is defined on values with integer type, values with pointer /// This function is defined on values with integer type, values with pointer
/// type (but only if TD is non-null), and vectors of integers. In the case /// type (but only if TD is non-null), and vectors of integers. In the case
/// where V is a vector, the known zero and known one values are the /// where V is a vector, the known zero and known one values are the
/// same width as the vector element, and the bit is set only if it is true /// same width as the vector element, and the bit is set only if it is true
/// for all of the elements in the vector. /// for all of the elements in the vector.
void ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne, void computeKnownBits(Value *V, APInt &KnownZero, APInt &KnownOne,
const DataLayout *TD = nullptr, unsigned Depth = 0); const DataLayout *TD = nullptr, unsigned Depth = 0);
void computeMaskedBitsLoad(const MDNode &Ranges, APInt &KnownZero); void computeKnownBitsLoad(const MDNode &Ranges, APInt &KnownZero);
/// ComputeSignBit - Determine whether the sign bit is known to be zero or /// ComputeSignBit - Determine whether the sign bit is known to be zero or
/// one. Convenience wrapper around ComputeMaskedBits. /// one. Convenience wrapper around computeKnownBits.
void ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne, void ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne,
const DataLayout *TD = nullptr, unsigned Depth = 0); const DataLayout *TD = nullptr, unsigned Depth = 0);

10
include/llvm/CodeGen/SelectionDAG.h
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@ -1079,11 +1079,11 @@ public:
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0) bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth = 0)
const; const;
/// ComputeMaskedBits - Determine which bits of Op are /// Determine which bits of Op are known to be either zero or one and return
/// known to be either zero or one and return them in the KnownZero/KnownOne /// them in the KnownZero/KnownOne bitsets. Targets can implement the
/// bitsets. Targets can implement the computeMaskedBitsForTargetNode /// computeKnownBitsForTargetNode method in the TargetLowering class to allow
/// method in the TargetLowering class to allow target nodes to be understood. /// target nodes to be understood.
void ComputeMaskedBits(SDValue Op, APInt &KnownZero, APInt &KnownOne, void computeKnownBits(SDValue Op, APInt &KnownZero, APInt &KnownOne,
unsigned Depth = 0) const; unsigned Depth = 0) const;
/// ComputeNumSignBits - Return the number of times the sign bit of the /// ComputeNumSignBits - Return the number of times the sign bit of the

2
include/llvm/Target/TargetLowering.h
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@ -1943,7 +1943,7 @@ public:
/// Determine which of the bits specified in Mask are known to be either zero /// Determine which of the bits specified in Mask are known to be either zero
/// or one and return them in the KnownZero/KnownOne bitsets. /// or one and return them in the KnownZero/KnownOne bitsets.
virtual void computeMaskedBitsForTargetNode(const SDValue Op, virtual void computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,

4
lib/Analysis/ConstantFolding.cpp
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@ -571,8 +571,8 @@ static Constant *SymbolicallyEvaluateBinop(unsigned Opc, Constant *Op0,
unsigned BitWidth = DL->getTypeSizeInBits(Op0->getType()->getScalarType()); unsigned BitWidth = DL->getTypeSizeInBits(Op0->getType()->getScalarType());
APInt KnownZero0(BitWidth, 0), KnownOne0(BitWidth, 0); APInt KnownZero0(BitWidth, 0), KnownOne0(BitWidth, 0);
APInt KnownZero1(BitWidth, 0), KnownOne1(BitWidth, 0); APInt KnownZero1(BitWidth, 0), KnownOne1(BitWidth, 0);
ComputeMaskedBits(Op0, KnownZero0, KnownOne0, DL); computeKnownBits(Op0, KnownZero0, KnownOne0, DL);
ComputeMaskedBits(Op1, KnownZero1, KnownOne1, DL); computeKnownBits(Op1, KnownZero1, KnownOne1, DL);
if ((KnownOne1 | KnownZero0).isAllOnesValue()) { if ((KnownOne1 | KnownZero0).isAllOnesValue()) {
// All the bits of Op0 that the 'and' could be masking are already zero. // All the bits of Op0 that the 'and' could be masking are already zero.
return Op0; return Op0;

4
lib/Analysis/Lint.cpp
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@ -513,7 +513,7 @@ static bool isZero(Value *V, const DataLayout *DL) {
if (!VecTy) { if (!VecTy) {
unsigned BitWidth = V->getType()->getIntegerBitWidth(); unsigned BitWidth = V->getType()->getIntegerBitWidth();
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(V, KnownZero, KnownOne, DL); computeKnownBits(V, KnownZero, KnownOne, DL);
return KnownZero.isAllOnesValue(); return KnownZero.isAllOnesValue();
} }
@ -534,7 +534,7 @@ static bool isZero(Value *V, const DataLayout *DL) {
return true; return true;
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(Elem, KnownZero, KnownOne, DL); computeKnownBits(Elem, KnownZero, KnownOne, DL);
if (KnownZero.isAllOnesValue()) if (KnownZero.isAllOnesValue())
return true; return true;
} }

8
lib/Analysis/ScalarEvolution.cpp
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@ -3362,7 +3362,7 @@ ScalarEvolution::GetMinTrailingZeros(const SCEV *S) {
// For a SCEVUnknown, ask ValueTracking. // For a SCEVUnknown, ask ValueTracking.
unsigned BitWidth = getTypeSizeInBits(U->getType()); unsigned BitWidth = getTypeSizeInBits(U->getType());
APInt Zeros(BitWidth, 0), Ones(BitWidth, 0); APInt Zeros(BitWidth, 0), Ones(BitWidth, 0);
ComputeMaskedBits(U->getValue(), Zeros, Ones); computeKnownBits(U->getValue(), Zeros, Ones);
return Zeros.countTrailingOnes(); return Zeros.countTrailingOnes();
} }
@ -3501,7 +3501,7 @@ ScalarEvolution::getUnsignedRange(const SCEV *S) {
if (const SCEVUnknown *U = dyn_cast<SCEVUnknown>(S)) { if (const SCEVUnknown *U = dyn_cast<SCEVUnknown>(S)) {
// For a SCEVUnknown, ask ValueTracking. // For a SCEVUnknown, ask ValueTracking.
APInt Zeros(BitWidth, 0), Ones(BitWidth, 0); APInt Zeros(BitWidth, 0), Ones(BitWidth, 0);
ComputeMaskedBits(U->getValue(), Zeros, Ones, DL); computeKnownBits(U->getValue(), Zeros, Ones, DL);
if (Ones == ~Zeros + 1) if (Ones == ~Zeros + 1)
return setUnsignedRange(U, ConservativeResult); return setUnsignedRange(U, ConservativeResult);
return setUnsignedRange(U, return setUnsignedRange(U,
@ -3754,13 +3754,13 @@ const SCEV *ScalarEvolution::createSCEV(Value *V) {
// Instcombine's ShrinkDemandedConstant may strip bits out of // Instcombine's ShrinkDemandedConstant may strip bits out of
// constants, obscuring what would otherwise be a low-bits mask. // constants, obscuring what would otherwise be a low-bits mask.
// Use ComputeMaskedBits to compute what ShrinkDemandedConstant // Use computeKnownBits to compute what ShrinkDemandedConstant
// knew about to reconstruct a low-bits mask value. // knew about to reconstruct a low-bits mask value.
unsigned LZ = A.countLeadingZeros(); unsigned LZ = A.countLeadingZeros();
unsigned TZ = A.countTrailingZeros(); unsigned TZ = A.countTrailingZeros();
unsigned BitWidth = A.getBitWidth(); unsigned BitWidth = A.getBitWidth();
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(U->getOperand(0), KnownZero, KnownOne, DL); computeKnownBits(U->getOperand(0), KnownZero, KnownOne, DL);
APInt EffectiveMask = APInt EffectiveMask =
APInt::getLowBitsSet(BitWidth, BitWidth - LZ - TZ).shl(TZ); APInt::getLowBitsSet(BitWidth, BitWidth - LZ - TZ).shl(TZ);

120
lib/Analysis/ValueTracking.cpp
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@ -44,7 +44,7 @@ static unsigned getBitWidth(Type *Ty, const DataLayout *TD) {
return TD ? TD->getPointerTypeSizeInBits(Ty) : 0; return TD ? TD->getPointerTypeSizeInBits(Ty) : 0;
} }
static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW, static void computeKnownBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
APInt &KnownZero, APInt &KnownOne, APInt &KnownZero, APInt &KnownOne,
APInt &KnownZero2, APInt &KnownOne2, APInt &KnownZero2, APInt &KnownOne2,
const DataLayout *TD, unsigned Depth) { const DataLayout *TD, unsigned Depth) {
@ -58,7 +58,7 @@ static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
unsigned NLZ = (CLHS->getValue()+1).countLeadingZeros(); unsigned NLZ = (CLHS->getValue()+1).countLeadingZeros();
// NLZ can't be BitWidth with no sign bit // NLZ can't be BitWidth with no sign bit
APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);
llvm::ComputeMaskedBits(Op1, KnownZero2, KnownOne2, TD, Depth+1); llvm::computeKnownBits(Op1, KnownZero2, KnownOne2, TD, Depth+1);
// If all of the MaskV bits are known to be zero, then we know the // If all of the MaskV bits are known to be zero, then we know the
// output top bits are zero, because we now know that the output is // output top bits are zero, because we now know that the output is
@ -79,12 +79,12 @@ static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
// result. For an add, this works with either operand. For a subtract, // result. For an add, this works with either operand. For a subtract,
// this only works if the known zeros are in the right operand. // this only works if the known zeros are in the right operand.
APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
llvm::ComputeMaskedBits(Op0, LHSKnownZero, LHSKnownOne, TD, Depth+1); llvm::computeKnownBits(Op0, LHSKnownZero, LHSKnownOne, TD, Depth+1);
assert((LHSKnownZero & LHSKnownOne) == 0 && assert((LHSKnownZero & LHSKnownOne) == 0 &&
"Bits known to be one AND zero?"); "Bits known to be one AND zero?");
unsigned LHSKnownZeroOut = LHSKnownZero.countTrailingOnes(); unsigned LHSKnownZeroOut = LHSKnownZero.countTrailingOnes();
llvm::ComputeMaskedBits(Op1, KnownZero2, KnownOne2, TD, Depth+1); llvm::computeKnownBits(Op1, KnownZero2, KnownOne2, TD, Depth+1);
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
unsigned RHSKnownZeroOut = KnownZero2.countTrailingOnes(); unsigned RHSKnownZeroOut = KnownZero2.countTrailingOnes();
@ -130,13 +130,13 @@ static void ComputeMaskedBitsAddSub(bool Add, Value *Op0, Value *Op1, bool NSW,
} }
} }
static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW, static void computeKnownBitsMul(Value *Op0, Value *Op1, bool NSW,
APInt &KnownZero, APInt &KnownOne, APInt &KnownZero, APInt &KnownOne,
APInt &KnownZero2, APInt &KnownOne2, APInt &KnownZero2, APInt &KnownOne2,
const DataLayout *TD, unsigned Depth) { const DataLayout *TD, unsigned Depth) {
unsigned BitWidth = KnownZero.getBitWidth(); unsigned BitWidth = KnownZero.getBitWidth();
ComputeMaskedBits(Op1, KnownZero, KnownOne, TD, Depth+1); computeKnownBits(Op1, KnownZero, KnownOne, TD, Depth+1);
ComputeMaskedBits(Op0, KnownZero2, KnownOne2, TD, Depth+1); computeKnownBits(Op0, KnownZero2, KnownOne2, TD, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -192,7 +192,7 @@ static void ComputeMaskedBitsMul(Value *Op0, Value *Op1, bool NSW,
KnownOne.setBit(BitWidth - 1); KnownOne.setBit(BitWidth - 1);
} }
void llvm::computeMaskedBitsLoad(const MDNode &Ranges, APInt &KnownZero) { void llvm::computeKnownBitsLoad(const MDNode &Ranges, APInt &KnownZero) {
unsigned BitWidth = KnownZero.getBitWidth(); unsigned BitWidth = KnownZero.getBitWidth();
unsigned NumRanges = Ranges.getNumOperands() / 2; unsigned NumRanges = Ranges.getNumOperands() / 2;
assert(NumRanges >= 1); assert(NumRanges >= 1);
@ -211,8 +211,8 @@ void llvm::computeMaskedBitsLoad(const MDNode &Ranges, APInt &KnownZero) {
KnownZero = APInt::getHighBitsSet(BitWidth, MinLeadingZeros); KnownZero = APInt::getHighBitsSet(BitWidth, MinLeadingZeros);
} }
/// ComputeMaskedBits - Determine which bits of V are known to be either zero /// Determine which bits of V are known to be either zero or one and return
/// or one and return them in the KnownZero/KnownOne bit sets. /// them in the KnownZero/KnownOne bit sets.
/// ///
/// NOTE: we cannot consider 'undef' to be "IsZero" here. The problem is that /// NOTE: we cannot consider 'undef' to be "IsZero" here. The problem is that
/// we cannot optimize based on the assumption that it is zero without changing /// we cannot optimize based on the assumption that it is zero without changing
@ -226,7 +226,7 @@ void llvm::computeMaskedBitsLoad(const MDNode &Ranges, APInt &KnownZero) {
/// where V is a vector, known zero, and known one values are the /// where V is a vector, known zero, and known one values are the
/// same width as the vector element, and the bit is set only if it is true /// same width as the vector element, and the bit is set only if it is true
/// for all of the elements in the vector. /// for all of the elements in the vector.
void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne, void llvm::computeKnownBits(Value *V, APInt &KnownZero, APInt &KnownOne,
const DataLayout *TD, unsigned Depth) { const DataLayout *TD, unsigned Depth) {
assert(V && "No Value?"); assert(V && "No Value?");
assert(Depth <= MaxDepth && "Limit Search Depth"); assert(Depth <= MaxDepth && "Limit Search Depth");
@ -303,7 +303,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
if (GA->mayBeOverridden()) { if (GA->mayBeOverridden()) {
KnownZero.clearAllBits(); KnownOne.clearAllBits(); KnownZero.clearAllBits(); KnownOne.clearAllBits();
} else { } else {
ComputeMaskedBits(GA->getAliasee(), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(GA->getAliasee(), KnownZero, KnownOne, TD, Depth+1);
} }
return; return;
} }
@ -341,12 +341,12 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
default: break; default: break;
case Instruction::Load: case Instruction::Load:
if (MDNode *MD = cast<LoadInst>(I)->getMetadata(LLVMContext::MD_range)) if (MDNode *MD = cast<LoadInst>(I)->getMetadata(LLVMContext::MD_range))
computeMaskedBitsLoad(*MD, KnownZero); computeKnownBitsLoad(*MD, KnownZero);
return; return;
case Instruction::And: { case Instruction::And: {
// If either the LHS or the RHS are Zero, the result is zero. // If either the LHS or the RHS are Zero, the result is zero.
ComputeMaskedBits(I->getOperand(1), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(1), KnownZero, KnownOne, TD, Depth+1);
ComputeMaskedBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -357,8 +357,8 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
return; return;
} }
case Instruction::Or: { case Instruction::Or: {
ComputeMaskedBits(I->getOperand(1), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(1), KnownZero, KnownOne, TD, Depth+1);
ComputeMaskedBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -369,8 +369,8 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
return; return;
} }
case Instruction::Xor: { case Instruction::Xor: {
ComputeMaskedBits(I->getOperand(1), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(1), KnownZero, KnownOne, TD, Depth+1);
ComputeMaskedBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -383,7 +383,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
} }
case Instruction::Mul: { case Instruction::Mul: {
bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap(); bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap();
ComputeMaskedBitsMul(I->getOperand(0), I->getOperand(1), NSW, computeKnownBitsMul(I->getOperand(0), I->getOperand(1), NSW,
KnownZero, KnownOne, KnownZero2, KnownOne2, TD, Depth); KnownZero, KnownOne, KnownZero2, KnownOne2, TD, Depth);
break; break;
} }
@ -391,12 +391,12 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
// For the purposes of computing leading zeros we can conservatively // For the purposes of computing leading zeros we can conservatively
// treat a udiv as a logical right shift by the power of 2 known to // treat a udiv as a logical right shift by the power of 2 known to
// be less than the denominator. // be less than the denominator.
ComputeMaskedBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1);
unsigned LeadZ = KnownZero2.countLeadingOnes(); unsigned LeadZ = KnownZero2.countLeadingOnes();
KnownOne2.clearAllBits(); KnownOne2.clearAllBits();
KnownZero2.clearAllBits(); KnownZero2.clearAllBits();
ComputeMaskedBits(I->getOperand(1), KnownZero2, KnownOne2, TD, Depth+1); computeKnownBits(I->getOperand(1), KnownZero2, KnownOne2, TD, Depth+1);
unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros();
if (RHSUnknownLeadingOnes != BitWidth) if (RHSUnknownLeadingOnes != BitWidth)
LeadZ = std::min(BitWidth, LeadZ = std::min(BitWidth,
@ -406,8 +406,8 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
return; return;
} }
case Instruction::Select: case Instruction::Select:
ComputeMaskedBits(I->getOperand(2), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(2), KnownZero, KnownOne, TD, Depth+1);
ComputeMaskedBits(I->getOperand(1), KnownZero2, KnownOne2, TD, computeKnownBits(I->getOperand(1), KnownZero2, KnownOne2, TD,
Depth+1); Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -445,7 +445,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
assert(SrcBitWidth && "SrcBitWidth can't be zero"); assert(SrcBitWidth && "SrcBitWidth can't be zero");
KnownZero = KnownZero.zextOrTrunc(SrcBitWidth); KnownZero = KnownZero.zextOrTrunc(SrcBitWidth);
KnownOne = KnownOne.zextOrTrunc(SrcBitWidth); KnownOne = KnownOne.zextOrTrunc(SrcBitWidth);
ComputeMaskedBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1);
KnownZero = KnownZero.zextOrTrunc(BitWidth); KnownZero = KnownZero.zextOrTrunc(BitWidth);
KnownOne = KnownOne.zextOrTrunc(BitWidth); KnownOne = KnownOne.zextOrTrunc(BitWidth);
// Any top bits are known to be zero. // Any top bits are known to be zero.
@ -459,7 +459,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
// TODO: For now, not handling conversions like: // TODO: For now, not handling conversions like:
// (bitcast i64 %x to <2 x i32>) // (bitcast i64 %x to <2 x i32>)
!I->getType()->isVectorTy()) { !I->getType()->isVectorTy()) {
ComputeMaskedBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1);
return; return;
} }
break; break;
@ -470,7 +470,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
KnownZero = KnownZero.trunc(SrcBitWidth); KnownZero = KnownZero.trunc(SrcBitWidth);
KnownOne = KnownOne.trunc(SrcBitWidth); KnownOne = KnownOne.trunc(SrcBitWidth);
ComputeMaskedBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero = KnownZero.zext(BitWidth); KnownZero = KnownZero.zext(BitWidth);
KnownOne = KnownOne.zext(BitWidth); KnownOne = KnownOne.zext(BitWidth);
@ -487,7 +487,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
// (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0 // (shl X, C1) & C2 == 0 iff (X & C2 >>u C1) == 0
if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) { if (ConstantInt *SA = dyn_cast<ConstantInt>(I->getOperand(1))) {
uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
ComputeMaskedBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero <<= ShiftAmt; KnownZero <<= ShiftAmt;
KnownOne <<= ShiftAmt; KnownOne <<= ShiftAmt;
@ -502,7 +502,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
// Unsigned shift right. // Unsigned shift right.
ComputeMaskedBits(I->getOperand(0), KnownZero,KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero,KnownOne, TD, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
KnownOne = APIntOps::lshr(KnownOne, ShiftAmt); KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
@ -518,7 +518,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
// Signed shift right. // Signed shift right.
ComputeMaskedBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
KnownOne = APIntOps::lshr(KnownOne, ShiftAmt); KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
@ -533,14 +533,14 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
break; break;
case Instruction::Sub: { case Instruction::Sub: {
bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap(); bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap();
ComputeMaskedBitsAddSub(false, I->getOperand(0), I->getOperand(1), NSW, computeKnownBitsAddSub(false, I->getOperand(0), I->getOperand(1), NSW,
KnownZero, KnownOne, KnownZero2, KnownOne2, TD, KnownZero, KnownOne, KnownZero2, KnownOne2, TD,
Depth); Depth);
break; break;
} }
case Instruction::Add: { case Instruction::Add: {
bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap(); bool NSW = cast<OverflowingBinaryOperator>(I)->hasNoSignedWrap();
ComputeMaskedBitsAddSub(true, I->getOperand(0), I->getOperand(1), NSW, computeKnownBitsAddSub(true, I->getOperand(0), I->getOperand(1), NSW,
KnownZero, KnownOne, KnownZero2, KnownOne2, TD, KnownZero, KnownOne, KnownZero2, KnownOne2, TD,
Depth); Depth);
break; break;
@ -550,7 +550,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
APInt RA = Rem->getValue().abs(); APInt RA = Rem->getValue().abs();
if (RA.isPowerOf2()) { if (RA.isPowerOf2()) {
APInt LowBits = RA - 1; APInt LowBits = RA - 1;
ComputeMaskedBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero2, KnownOne2, TD, Depth+1);
// The low bits of the first operand are unchanged by the srem. // The low bits of the first operand are unchanged by the srem.
KnownZero = KnownZero2 & LowBits; KnownZero = KnownZero2 & LowBits;
@ -574,7 +574,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
// remainder is zero. // remainder is zero.
if (KnownZero.isNonNegative()) { if (KnownZero.isNonNegative()) {
APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, TD, computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, TD,
Depth+1); Depth+1);
// If it's known zero, our sign bit is also zero. // If it's known zero, our sign bit is also zero.
if (LHSKnownZero.isNegative()) if (LHSKnownZero.isNegative())
@ -587,7 +587,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
APInt RA = Rem->getValue(); APInt RA = Rem->getValue();
if (RA.isPowerOf2()) { if (RA.isPowerOf2()) {
APInt LowBits = (RA - 1); APInt LowBits = (RA - 1);
ComputeMaskedBits(I->getOperand(0), KnownZero, KnownOne, TD, computeKnownBits(I->getOperand(0), KnownZero, KnownOne, TD,
Depth+1); Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero |= ~LowBits; KnownZero |= ~LowBits;
@ -598,8 +598,8 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
// Since the result is less than or equal to either operand, any leading // Since the result is less than or equal to either operand, any leading
// zero bits in either operand must also exist in the result. // zero bits in either operand must also exist in the result.
ComputeMaskedBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(I->getOperand(0), KnownZero, KnownOne, TD, Depth+1);
ComputeMaskedBits(I->getOperand(1), KnownZero2, KnownOne2, TD, Depth+1); computeKnownBits(I->getOperand(1), KnownZero2, KnownOne2, TD, Depth+1);
unsigned Leaders = std::max(KnownZero.countLeadingOnes(), unsigned Leaders = std::max(KnownZero.countLeadingOnes(),
KnownZero2.countLeadingOnes()); KnownZero2.countLeadingOnes());
@ -622,7 +622,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
// Analyze all of the subscripts of this getelementptr instruction // Analyze all of the subscripts of this getelementptr instruction
// to determine if we can prove known low zero bits. // to determine if we can prove known low zero bits.
APInt LocalKnownZero(BitWidth, 0), LocalKnownOne(BitWidth, 0); APInt LocalKnownZero(BitWidth, 0), LocalKnownOne(BitWidth, 0);
ComputeMaskedBits(I->getOperand(0), LocalKnownZero, LocalKnownOne, TD, computeKnownBits(I->getOperand(0), LocalKnownZero, LocalKnownOne, TD,
Depth+1); Depth+1);
unsigned TrailZ = LocalKnownZero.countTrailingOnes(); unsigned TrailZ = LocalKnownZero.countTrailingOnes();
@ -654,7 +654,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
unsigned GEPOpiBits = Index->getType()->getScalarSizeInBits(); unsigned GEPOpiBits = Index->getType()->getScalarSizeInBits();
uint64_t TypeSize = TD ? TD->getTypeAllocSize(IndexedTy) : 1; uint64_t TypeSize = TD ? TD->getTypeAllocSize(IndexedTy) : 1;
LocalKnownZero = LocalKnownOne = APInt(GEPOpiBits, 0); LocalKnownZero = LocalKnownOne = APInt(GEPOpiBits, 0);
ComputeMaskedBits(Index, LocalKnownZero, LocalKnownOne, TD, Depth+1); computeKnownBits(Index, LocalKnownZero, LocalKnownOne, TD, Depth+1);
TrailZ = std::min(TrailZ, TrailZ = std::min(TrailZ,
unsigned(countTrailingZeros(TypeSize) + unsigned(countTrailingZeros(TypeSize) +
LocalKnownZero.countTrailingOnes())); LocalKnownZero.countTrailingOnes()));
@ -696,11 +696,11 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
break; break;
// Ok, we have a PHI of the form L op= R. Check for low // Ok, we have a PHI of the form L op= R. Check for low
// zero bits. // zero bits.
ComputeMaskedBits(R, KnownZero2, KnownOne2, TD, Depth+1); computeKnownBits(R, KnownZero2, KnownOne2, TD, Depth+1);
// We need to take the minimum number of known bits // We need to take the minimum number of known bits
APInt KnownZero3(KnownZero), KnownOne3(KnownOne); APInt KnownZero3(KnownZero), KnownOne3(KnownOne);
ComputeMaskedBits(L, KnownZero3, KnownOne3, TD, Depth+1); computeKnownBits(L, KnownZero3, KnownOne3, TD, Depth+1);
KnownZero = APInt::getLowBitsSet(BitWidth, KnownZero = APInt::getLowBitsSet(BitWidth,
std::min(KnownZero2.countTrailingOnes(), std::min(KnownZero2.countTrailingOnes(),
@ -731,7 +731,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
KnownOne2 = APInt(BitWidth, 0); KnownOne2 = APInt(BitWidth, 0);
// Recurse, but cap the recursion to one level, because we don't // Recurse, but cap the recursion to one level, because we don't
// want to waste time spinning around in loops. // want to waste time spinning around in loops.
ComputeMaskedBits(P->getIncomingValue(i), KnownZero2, KnownOne2, TD, computeKnownBits(P->getIncomingValue(i), KnownZero2, KnownOne2, TD,
MaxDepth-1); MaxDepth-1);
KnownZero &= KnownZero2; KnownZero &= KnownZero2;
KnownOne &= KnownOne2; KnownOne &= KnownOne2;
@ -776,19 +776,19 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
default: break; default: break;
case Intrinsic::uadd_with_overflow: case Intrinsic::uadd_with_overflow:
case Intrinsic::sadd_with_overflow: case Intrinsic::sadd_with_overflow:
ComputeMaskedBitsAddSub(true, II->getArgOperand(0), computeKnownBitsAddSub(true, II->getArgOperand(0),
II->getArgOperand(1), false, KnownZero, II->getArgOperand(1), false, KnownZero,
KnownOne, KnownZero2, KnownOne2, TD, Depth); KnownOne, KnownZero2, KnownOne2, TD, Depth);
break; break;
case Intrinsic::usub_with_overflow: case Intrinsic::usub_with_overflow:
case Intrinsic::ssub_with_overflow: case Intrinsic::ssub_with_overflow:
ComputeMaskedBitsAddSub(false, II->getArgOperand(0), computeKnownBitsAddSub(false, II->getArgOperand(0),
II->getArgOperand(1), false, KnownZero, II->getArgOperand(1), false, KnownZero,
KnownOne, KnownZero2, KnownOne2, TD, Depth); KnownOne, KnownZero2, KnownOne2, TD, Depth);
break; break;
case Intrinsic::umul_with_overflow: case Intrinsic::umul_with_overflow:
case Intrinsic::smul_with_overflow: case Intrinsic::smul_with_overflow:
ComputeMaskedBitsMul(II->getArgOperand(0), II->getArgOperand(1), computeKnownBitsMul(II->getArgOperand(0), II->getArgOperand(1),
false, KnownZero, KnownOne, false, KnownZero, KnownOne,
KnownZero2, KnownOne2, TD, Depth); KnownZero2, KnownOne2, TD, Depth);
break; break;
@ -799,7 +799,7 @@ void llvm::ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne,
} }
/// ComputeSignBit - Determine whether the sign bit is known to be zero or /// ComputeSignBit - Determine whether the sign bit is known to be zero or
/// one. Convenience wrapper around ComputeMaskedBits. /// one. Convenience wrapper around computeKnownBits.
void llvm::ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne, void llvm::ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne,
const DataLayout *TD, unsigned Depth) { const DataLayout *TD, unsigned Depth) {
unsigned BitWidth = getBitWidth(V->getType(), TD); unsigned BitWidth = getBitWidth(V->getType(), TD);
@ -810,7 +810,7 @@ void llvm::ComputeSignBit(Value *V, bool &KnownZero, bool &KnownOne,
} }
APInt ZeroBits(BitWidth, 0); APInt ZeroBits(BitWidth, 0);
APInt OneBits(BitWidth, 0); APInt OneBits(BitWidth, 0);
ComputeMaskedBits(V, ZeroBits, OneBits, TD, Depth); computeKnownBits(V, ZeroBits, OneBits, TD, Depth);
KnownOne = OneBits[BitWidth - 1]; KnownOne = OneBits[BitWidth - 1];
KnownZero = ZeroBits[BitWidth - 1]; KnownZero = ZeroBits[BitWidth - 1];
} }
@ -882,10 +882,10 @@ bool llvm::isKnownToBeAPowerOfTwo(Value *V, bool OrZero, unsigned Depth) {
unsigned BitWidth = V->getType()->getScalarSizeInBits(); unsigned BitWidth = V->getType()->getScalarSizeInBits();
APInt LHSZeroBits(BitWidth, 0), LHSOneBits(BitWidth, 0); APInt LHSZeroBits(BitWidth, 0), LHSOneBits(BitWidth, 0);
ComputeMaskedBits(X, LHSZeroBits, LHSOneBits, nullptr, Depth); computeKnownBits(X, LHSZeroBits, LHSOneBits, nullptr, Depth);
APInt RHSZeroBits(BitWidth, 0), RHSOneBits(BitWidth, 0); APInt RHSZeroBits(BitWidth, 0), RHSOneBits(BitWidth, 0);
ComputeMaskedBits(Y, RHSZeroBits, RHSOneBits, nullptr, Depth); computeKnownBits(Y, RHSZeroBits, RHSOneBits, nullptr, Depth);
// If i8 V is a power of two or zero: // If i8 V is a power of two or zero:
// ZeroBits: 1 1 1 0 1 1 1 1 // ZeroBits: 1 1 1 0 1 1 1 1
// ~ZeroBits: 0 0 0 1 0 0 0 0 // ~ZeroBits: 0 0 0 1 0 0 0 0
@ -1023,7 +1023,7 @@ bool llvm::isKnownNonZero(Value *V, const DataLayout *TD, unsigned Depth) {
APInt KnownZero(BitWidth, 0); APInt KnownZero(BitWidth, 0);
APInt KnownOne(BitWidth, 0); APInt KnownOne(BitWidth, 0);
ComputeMaskedBits(X, KnownZero, KnownOne, TD, Depth); computeKnownBits(X, KnownZero, KnownOne, TD, Depth);
if (KnownOne[0]) if (KnownOne[0])
return true; return true;
} }
@ -1065,12 +1065,12 @@ bool llvm::isKnownNonZero(Value *V, const DataLayout *TD, unsigned Depth) {
APInt Mask = APInt::getSignedMaxValue(BitWidth); APInt Mask = APInt::getSignedMaxValue(BitWidth);
// The sign bit of X is set. If some other bit is set then X is not equal // The sign bit of X is set. If some other bit is set then X is not equal
// to INT_MIN. // to INT_MIN.
ComputeMaskedBits(X, KnownZero, KnownOne, TD, Depth); computeKnownBits(X, KnownZero, KnownOne, TD, Depth);
if ((KnownOne & Mask) != 0) if ((KnownOne & Mask) != 0)
return true; return true;
// The sign bit of Y is set. If some other bit is set then Y is not equal // The sign bit of Y is set. If some other bit is set then Y is not equal
// to INT_MIN. // to INT_MIN.
ComputeMaskedBits(Y, KnownZero, KnownOne, TD, Depth); computeKnownBits(Y, KnownZero, KnownOne, TD, Depth);
if ((KnownOne & Mask) != 0) if ((KnownOne & Mask) != 0)
return true; return true;
} }
@ -1100,7 +1100,7 @@ bool llvm::isKnownNonZero(Value *V, const DataLayout *TD, unsigned Depth) {
if (!BitWidth) return false; if (!BitWidth) return false;
APInt KnownZero(BitWidth, 0); APInt KnownZero(BitWidth, 0);
APInt KnownOne(BitWidth, 0); APInt KnownOne(BitWidth, 0);
ComputeMaskedBits(V, KnownZero, KnownOne, TD, Depth); computeKnownBits(V, KnownZero, KnownOne, TD, Depth);
return KnownOne != 0; return KnownOne != 0;
} }
@ -1116,7 +1116,7 @@ bool llvm::isKnownNonZero(Value *V, const DataLayout *TD, unsigned Depth) {
bool llvm::MaskedValueIsZero(Value *V, const APInt &Mask, bool llvm::MaskedValueIsZero(Value *V, const APInt &Mask,
const DataLayout *TD, unsigned Depth) { const DataLayout *TD, unsigned Depth) {
APInt KnownZero(Mask.getBitWidth(), 0), KnownOne(Mask.getBitWidth(), 0); APInt KnownZero(Mask.getBitWidth(), 0), KnownOne(Mask.getBitWidth(), 0);
ComputeMaskedBits(V, KnownZero, KnownOne, TD, Depth); computeKnownBits(V, KnownZero, KnownOne, TD, Depth);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
return (KnownZero & Mask) == Mask; return (KnownZero & Mask) == Mask;
} }
@ -1142,7 +1142,7 @@ unsigned llvm::ComputeNumSignBits(Value *V, const DataLayout *TD,
unsigned Tmp, Tmp2; unsigned Tmp, Tmp2;
unsigned FirstAnswer = 1; unsigned FirstAnswer = 1;
// Note that ConstantInt is handled by the general ComputeMaskedBits case // Note that ConstantInt is handled by the general computeKnownBits case
// below. // below.
if (Depth == 6) if (Depth == 6)
@ -1187,7 +1187,7 @@ unsigned llvm::ComputeNumSignBits(Value *V, const DataLayout *TD,
FirstAnswer = std::min(Tmp, Tmp2); FirstAnswer = std::min(Tmp, Tmp2);
// We computed what we know about the sign bits as our first // We computed what we know about the sign bits as our first
// answer. Now proceed to the generic code that uses // answer. Now proceed to the generic code that uses
// ComputeMaskedBits, and pick whichever answer is better. // computeKnownBits, and pick whichever answer is better.
} }
break; break;
@ -1207,7 +1207,7 @@ unsigned llvm::ComputeNumSignBits(Value *V, const DataLayout *TD,
if (ConstantInt *CRHS = dyn_cast<ConstantInt>(U->getOperand(1))) if (ConstantInt *CRHS = dyn_cast<ConstantInt>(U->getOperand(1)))
if (CRHS->isAllOnesValue()) { if (CRHS->isAllOnesValue()) {
APInt KnownZero(TyBits, 0), KnownOne(TyBits, 0); APInt KnownZero(TyBits, 0), KnownOne(TyBits, 0);
ComputeMaskedBits(U->getOperand(0), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(U->getOperand(0), KnownZero, KnownOne, TD, Depth+1);
// If the input is known to be 0 or 1, the output is 0/-1, which is all // If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set. // sign bits set.
@ -1232,7 +1232,7 @@ unsigned llvm::ComputeNumSignBits(Value *V, const DataLayout *TD,
if (ConstantInt *CLHS = dyn_cast<ConstantInt>(U->getOperand(0))) if (ConstantInt *CLHS = dyn_cast<ConstantInt>(U->getOperand(0)))
if (CLHS->isNullValue()) { if (CLHS->isNullValue()) {
APInt KnownZero(TyBits, 0), KnownOne(TyBits, 0); APInt KnownZero(TyBits, 0), KnownOne(TyBits, 0);
ComputeMaskedBits(U->getOperand(1), KnownZero, KnownOne, TD, Depth+1); computeKnownBits(U->getOperand(1), KnownZero, KnownOne, TD, Depth+1);
// If the input is known to be 0 or 1, the output is 0/-1, which is all // If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set. // sign bits set.
if ((KnownZero | APInt(TyBits, 1)).isAllOnesValue()) if ((KnownZero | APInt(TyBits, 1)).isAllOnesValue())
@ -1278,7 +1278,7 @@ unsigned llvm::ComputeNumSignBits(Value *V, const DataLayout *TD,
// use this information. // use this information.
APInt KnownZero(TyBits, 0), KnownOne(TyBits, 0); APInt KnownZero(TyBits, 0), KnownOne(TyBits, 0);
APInt Mask; APInt Mask;
ComputeMaskedBits(V, KnownZero, KnownOne, TD, Depth); computeKnownBits(V, KnownZero, KnownOne, TD, Depth);
if (KnownZero.isNegative()) { // sign bit is 0 if (KnownZero.isNegative()) { // sign bit is 0
Mask = KnownZero; Mask = KnownZero;
@ -2001,7 +2001,7 @@ bool llvm::isSafeToSpeculativelyExecute(const Value *V,
return false; return false;
APInt KnownZero(BitWidth, 0); APInt KnownZero(BitWidth, 0);
APInt KnownOne(BitWidth, 0); APInt KnownOne(BitWidth, 0);
ComputeMaskedBits(Op, KnownZero, KnownOne, TD); computeKnownBits(Op, KnownZero, KnownOne, TD);
return !!KnownZero; return !!KnownZero;
} }
case Instruction::Load: { case Instruction::Load: {

16
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
View File

@ -1564,10 +1564,10 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
if (VT.isInteger() && !VT.isVector()) { if (VT.isInteger() && !VT.isVector()) {
APInt LHSZero, LHSOne; APInt LHSZero, LHSOne;
APInt RHSZero, RHSOne; APInt RHSZero, RHSOne;
DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); DAG.computeKnownBits(N0, LHSZero, LHSOne);
if (LHSZero.getBoolValue()) { if (LHSZero.getBoolValue()) {
DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); DAG.computeKnownBits(N1, RHSZero, RHSOne);
// If all possibly-set bits on the LHS are clear on the RHS, return an OR. // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
// If all possibly-set bits on the RHS are clear on the LHS, return an OR. // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
@ -1659,10 +1659,10 @@ SDValue DAGCombiner::visitADDC(SDNode *N) {
// fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits. // fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
APInt LHSZero, LHSOne; APInt LHSZero, LHSOne;
APInt RHSZero, RHSOne; APInt RHSZero, RHSOne;
DAG.ComputeMaskedBits(N0, LHSZero, LHSOne); DAG.computeKnownBits(N0, LHSZero, LHSOne);
if (LHSZero.getBoolValue()) { if (LHSZero.getBoolValue()) {
DAG.ComputeMaskedBits(N1, RHSZero, RHSOne); DAG.computeKnownBits(N1, RHSZero, RHSOne);
// If all possibly-set bits on the LHS are clear on the RHS, return an OR. // If all possibly-set bits on the LHS are clear on the RHS, return an OR.
// If all possibly-set bits on the RHS are clear on the LHS, return an OR. // If all possibly-set bits on the RHS are clear on the LHS, return an OR.
@ -4348,7 +4348,7 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
if (N1C && N0.getOpcode() == ISD::CTLZ && if (N1C && N0.getOpcode() == ISD::CTLZ &&
N1C->getAPIntValue() == Log2_32(OpSizeInBits)) { N1C->getAPIntValue() == Log2_32(OpSizeInBits)) {
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(N0.getOperand(0), KnownZero, KnownOne); DAG.computeKnownBits(N0.getOperand(0), KnownZero, KnownOne);
// If any of the input bits are KnownOne, then the input couldn't be all // If any of the input bits are KnownOne, then the input couldn't be all
// zeros, thus the result of the srl will always be zero. // zeros, thus the result of the srl will always be zero.
@ -5074,13 +5074,13 @@ SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
// isTruncateOf - If N is a truncate of some other value, return true, record // isTruncateOf - If N is a truncate of some other value, return true, record
// the value being truncated in Op and which of Op's bits are zero in KnownZero. // the value being truncated in Op and which of Op's bits are zero in KnownZero.
// This function computes KnownZero to avoid a duplicated call to // This function computes KnownZero to avoid a duplicated call to
// ComputeMaskedBits in the caller. // computeKnownBits in the caller.
static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op, static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
APInt &KnownZero) { APInt &KnownZero) {
APInt KnownOne; APInt KnownOne;
if (N->getOpcode() == ISD::TRUNCATE) { if (N->getOpcode() == ISD::TRUNCATE) {
Op = N->getOperand(0); Op = N->getOperand(0);
DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); DAG.computeKnownBits(Op, KnownZero, KnownOne);
return true; return true;
} }
@ -5101,7 +5101,7 @@ static bool isTruncateOf(SelectionDAG &DAG, SDValue N, SDValue &Op,
else else
return false; return false;
DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); DAG.computeKnownBits(Op, KnownZero, KnownOne);
if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue()) if (!(KnownZero | APInt(Op.getValueSizeInBits(), 1)).isAllOnesValue())
return false; return false;

2
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
View File

@ -1375,7 +1375,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits));
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(N->getOperand(1), KnownZero, KnownOne); DAG.computeKnownBits(N->getOperand(1), KnownZero, KnownOne);
// If we don't know anything about the high bits, exit. // If we don't know anything about the high bits, exit.
if (((KnownZero|KnownOne) & HighBitMask) == 0) if (((KnownZero|KnownOne) & HighBitMask) == 0)

83
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -1807,15 +1807,14 @@ bool SelectionDAG::SignBitIsZero(SDValue Op, unsigned Depth) const {
bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask, bool SelectionDAG::MaskedValueIsZero(SDValue Op, const APInt &Mask,
unsigned Depth) const { unsigned Depth) const {
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); computeKnownBits(Op, KnownZero, KnownOne, Depth);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
return (KnownZero & Mask) == Mask; return (KnownZero & Mask) == Mask;
} }
/// ComputeMaskedBits - Determine which bits of Op are /// Determine which bits of Op are known to be either zero or one and return
/// known to be either zero or one and return them in the KnownZero/KnownOne /// them in the KnownZero/KnownOne bitsets.
/// bitsets. void SelectionDAG::computeKnownBits(SDValue Op, APInt &KnownZero,
void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
APInt &KnownOne, unsigned Depth) const { APInt &KnownOne, unsigned Depth) const {
const TargetLowering *TLI = TM.getTargetLowering(); const TargetLowering *TLI = TM.getTargetLowering();
unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits(); unsigned BitWidth = Op.getValueType().getScalarType().getSizeInBits();
@ -1834,8 +1833,8 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
return; return;
case ISD::AND: case ISD::AND:
// If either the LHS or the RHS are Zero, the result is zero. // If either the LHS or the RHS are Zero, the result is zero.
ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -1845,8 +1844,8 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
KnownZero |= KnownZero2; KnownZero |= KnownZero2;
return; return;
case ISD::OR: case ISD::OR:
ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -1856,8 +1855,8 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
KnownOne |= KnownOne2; KnownOne |= KnownOne2;
return; return;
case ISD::XOR: { case ISD::XOR: {
ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -1869,8 +1868,8 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
return; return;
} }
case ISD::MUL: { case ISD::MUL: {
ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -1895,12 +1894,12 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
// For the purposes of computing leading zeros we can conservatively // For the purposes of computing leading zeros we can conservatively
// treat a udiv as a logical right shift by the power of 2 known to // treat a udiv as a logical right shift by the power of 2 known to
// be less than the denominator. // be less than the denominator.
ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
unsigned LeadZ = KnownZero2.countLeadingOnes(); unsigned LeadZ = KnownZero2.countLeadingOnes();
KnownOne2.clearAllBits(); KnownOne2.clearAllBits();
KnownZero2.clearAllBits(); KnownZero2.clearAllBits();
ComputeMaskedBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1);
unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros(); unsigned RHSUnknownLeadingOnes = KnownOne2.countLeadingZeros();
if (RHSUnknownLeadingOnes != BitWidth) if (RHSUnknownLeadingOnes != BitWidth)
LeadZ = std::min(BitWidth, LeadZ = std::min(BitWidth,
@ -1910,8 +1909,8 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
return; return;
} }
case ISD::SELECT: case ISD::SELECT:
ComputeMaskedBits(Op.getOperand(2), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(2), KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -1920,8 +1919,8 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
KnownZero &= KnownZero2; KnownZero &= KnownZero2;
return; return;
case ISD::SELECT_CC: case ISD::SELECT_CC:
ComputeMaskedBits(Op.getOperand(3), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(3), KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(2), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(2), KnownZero2, KnownOne2, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
@ -1953,7 +1952,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
if (ShAmt >= BitWidth) if (ShAmt >= BitWidth)
return; return;
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero <<= ShAmt; KnownZero <<= ShAmt;
KnownOne <<= ShAmt; KnownOne <<= ShAmt;
@ -1970,7 +1969,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
if (ShAmt >= BitWidth) if (ShAmt >= BitWidth)
return; return;
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero = KnownZero.lshr(ShAmt); KnownZero = KnownZero.lshr(ShAmt);
KnownOne = KnownOne.lshr(ShAmt); KnownOne = KnownOne.lshr(ShAmt);
@ -1991,7 +1990,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
// demand the input sign bit. // demand the input sign bit.
APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt); APInt HighBits = APInt::getHighBitsSet(BitWidth, ShAmt);
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero = KnownZero.lshr(ShAmt); KnownZero = KnownZero.lshr(ShAmt);
KnownOne = KnownOne.lshr(ShAmt); KnownOne = KnownOne.lshr(ShAmt);
@ -2024,7 +2023,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
if (NewBits.getBoolValue()) if (NewBits.getBoolValue())
InputDemandedBits |= InSignBit; InputDemandedBits |= InSignBit;
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
KnownOne &= InputDemandedBits; KnownOne &= InputDemandedBits;
KnownZero &= InputDemandedBits; KnownZero &= InputDemandedBits;
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
@ -2061,7 +2060,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
unsigned MemBits = VT.getScalarType().getSizeInBits(); unsigned MemBits = VT.getScalarType().getSizeInBits();
KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits); KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits);
} else if (const MDNode *Ranges = LD->getRanges()) { } else if (const MDNode *Ranges = LD->getRanges()) {
computeMaskedBitsLoad(*Ranges, KnownZero); computeKnownBitsLoad(*Ranges, KnownZero);
} }
return; return;
} }
@ -2071,7 +2070,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits); APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits);
KnownZero = KnownZero.trunc(InBits); KnownZero = KnownZero.trunc(InBits);
KnownOne = KnownOne.trunc(InBits); KnownOne = KnownOne.trunc(InBits);
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
KnownZero = KnownZero.zext(BitWidth); KnownZero = KnownZero.zext(BitWidth);
KnownOne = KnownOne.zext(BitWidth); KnownOne = KnownOne.zext(BitWidth);
KnownZero |= NewBits; KnownZero |= NewBits;
@ -2084,7 +2083,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
KnownZero = KnownZero.trunc(InBits); KnownZero = KnownZero.trunc(InBits);
KnownOne = KnownOne.trunc(InBits); KnownOne = KnownOne.trunc(InBits);
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
// Note if the sign bit is known to be zero or one. // Note if the sign bit is known to be zero or one.
bool SignBitKnownZero = KnownZero.isNegative(); bool SignBitKnownZero = KnownZero.isNegative();
@ -2107,7 +2106,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
unsigned InBits = InVT.getScalarType().getSizeInBits(); unsigned InBits = InVT.getScalarType().getSizeInBits();
KnownZero = KnownZero.trunc(InBits); KnownZero = KnownZero.trunc(InBits);
KnownOne = KnownOne.trunc(InBits); KnownOne = KnownOne.trunc(InBits);
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
KnownZero = KnownZero.zext(BitWidth); KnownZero = KnownZero.zext(BitWidth);
KnownOne = KnownOne.zext(BitWidth); KnownOne = KnownOne.zext(BitWidth);
return; return;
@ -2117,7 +2116,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
unsigned InBits = InVT.getScalarType().getSizeInBits(); unsigned InBits = InVT.getScalarType().getSizeInBits();
KnownZero = KnownZero.zext(InBits); KnownZero = KnownZero.zext(InBits);
KnownOne = KnownOne.zext(InBits); KnownOne = KnownOne.zext(InBits);
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
KnownZero = KnownZero.trunc(BitWidth); KnownZero = KnownZero.trunc(BitWidth);
KnownOne = KnownOne.trunc(BitWidth); KnownOne = KnownOne.trunc(BitWidth);
@ -2126,7 +2125,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
case ISD::AssertZext: { case ISD::AssertZext: {
EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT(); EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits()); APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
KnownZero |= (~InMask); KnownZero |= (~InMask);
KnownOne &= (~KnownZero); KnownOne &= (~KnownZero);
return; return;
@ -2145,7 +2144,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros(); unsigned NLZ = (CLHS->getAPIntValue()+1).countLeadingZeros();
// NLZ can't be BitWidth with no sign bit // NLZ can't be BitWidth with no sign bit
APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1); APInt MaskV = APInt::getHighBitsSet(BitWidth, NLZ+1);
ComputeMaskedBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1);
// If all of the MaskV bits are known to be zero, then we know the // If all of the MaskV bits are known to be zero, then we know the
// output top bits are zero, because we now know that the output is // output top bits are zero, because we now know that the output is
@ -2164,11 +2163,11 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
// Output known-0 bits are known if clear or set in both the low clear bits // Output known-0 bits are known if clear or set in both the low clear bits
// common to both LHS & RHS. For example, 8+(X<<3) is known to have the // common to both LHS & RHS. For example, 8+(X<<3) is known to have the
// low 3 bits clear. // low 3 bits clear.
ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
unsigned KnownZeroOut = KnownZero2.countTrailingOnes(); unsigned KnownZeroOut = KnownZero2.countTrailingOnes();
ComputeMaskedBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1);
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");
KnownZeroOut = std::min(KnownZeroOut, KnownZeroOut = std::min(KnownZeroOut,
KnownZero2.countTrailingOnes()); KnownZero2.countTrailingOnes());
@ -2191,7 +2190,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
const APInt &RA = Rem->getAPIntValue().abs(); const APInt &RA = Rem->getAPIntValue().abs();
if (RA.isPowerOf2()) { if (RA.isPowerOf2()) {
APInt LowBits = RA - 1; APInt LowBits = RA - 1;
ComputeMaskedBits(Op.getOperand(0), KnownZero2,KnownOne2,Depth+1); computeKnownBits(Op.getOperand(0), KnownZero2,KnownOne2,Depth+1);
// The low bits of the first operand are unchanged by the srem. // The low bits of the first operand are unchanged by the srem.
KnownZero = KnownZero2 & LowBits; KnownZero = KnownZero2 & LowBits;
@ -2216,7 +2215,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
if (RA.isPowerOf2()) { if (RA.isPowerOf2()) {
APInt LowBits = (RA - 1); APInt LowBits = (RA - 1);
KnownZero |= ~LowBits; KnownZero |= ~LowBits;
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne,Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne,Depth+1);
assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
break; break;
} }
@ -2224,8 +2223,8 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
// Since the result is less than or equal to either operand, any leading // Since the result is less than or equal to either operand, any leading
// zero bits in either operand must also exist in the result. // zero bits in either operand must also exist in the result.
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
ComputeMaskedBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero2, KnownOne2, Depth+1);
uint32_t Leaders = std::max(KnownZero.countLeadingOnes(), uint32_t Leaders = std::max(KnownZero.countLeadingOnes(),
KnownZero2.countLeadingOnes()); KnownZero2.countLeadingOnes());
@ -2250,7 +2249,7 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, APInt &KnownZero,
case ISD::INTRINSIC_W_CHAIN: case ISD::INTRINSIC_W_CHAIN:
case ISD::INTRINSIC_VOID: case ISD::INTRINSIC_VOID:
// Allow the target to implement this method for its nodes. // Allow the target to implement this method for its nodes.
TLI->computeMaskedBitsForTargetNode(Op, KnownZero, KnownOne, *this, Depth); TLI->computeKnownBitsForTargetNode(Op, KnownZero, KnownOne, *this, Depth);
return; return;
} }
} }
@ -2326,7 +2325,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
FirstAnswer = std::min(Tmp, Tmp2); FirstAnswer = std::min(Tmp, Tmp2);
// We computed what we know about the sign bits as our first // We computed what we know about the sign bits as our first
// answer. Now proceed to the generic code that uses // answer. Now proceed to the generic code that uses
// ComputeMaskedBits, and pick whichever answer is better. // computeKnownBits, and pick whichever answer is better.
} }
break; break;
@ -2376,7 +2375,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) if (ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
if (CRHS->isAllOnesValue()) { if (CRHS->isAllOnesValue()) {
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
// If the input is known to be 0 or 1, the output is 0/-1, which is all // If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set. // sign bits set.
@ -2401,7 +2400,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0))) if (ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(Op.getOperand(0)))
if (CLHS->isNullValue()) { if (CLHS->isNullValue()) {
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
// If the input is known to be 0 or 1, the output is 0/-1, which is all // If the input is known to be 0 or 1, the output is 0/-1, which is all
// sign bits set. // sign bits set.
if ((KnownZero | APInt(VTBits, 1)).isAllOnesValue()) if ((KnownZero | APInt(VTBits, 1)).isAllOnesValue())
@ -2455,7 +2454,7 @@ unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
// Finally, if we can prove that the top bits of the result are 0's or 1's, // Finally, if we can prove that the top bits of the result are 0's or 1's,
// use this information. // use this information.
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); computeKnownBits(Op, KnownZero, KnownOne, Depth);
APInt Mask; APInt Mask;
if (KnownZero.isNegative()) { // sign bit is 0 if (KnownZero.isNegative()) { // sign bit is 0
@ -6424,7 +6423,7 @@ unsigned SelectionDAG::InferPtrAlignment(SDValue Ptr) const {
if (TLI->isGAPlusOffset(Ptr.getNode(), GV, GVOffset)) { if (TLI->isGAPlusOffset(Ptr.getNode(), GV, GVOffset)) {
unsigned PtrWidth = TLI->getPointerTypeSizeInBits(GV->getType()); unsigned PtrWidth = TLI->getPointerTypeSizeInBits(GV->getType());
APInt KnownZero(PtrWidth, 0), KnownOne(PtrWidth, 0); APInt KnownZero(PtrWidth, 0), KnownOne(PtrWidth, 0);
llvm::ComputeMaskedBits(const_cast<GlobalValue*>(GV), KnownZero, KnownOne, llvm::computeKnownBits(const_cast<GlobalValue*>(GV), KnownZero, KnownOne,
TLI->getDataLayout()); TLI->getDataLayout());
unsigned AlignBits = KnownZero.countTrailingOnes(); unsigned AlignBits = KnownZero.countTrailingOnes();
unsigned Align = AlignBits ? 1 << std::min(31U, AlignBits) : 0; unsigned Align = AlignBits ? 1 << std::min(31U, AlignBits) : 0;

4
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -621,7 +621,7 @@ void SelectionDAGISel::ComputeLiveOutVRegInfo() {
continue; continue;
unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); CurDAG->computeKnownBits(Src, KnownZero, KnownOne);
FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne);
} while (!Worklist.empty()); } while (!Worklist.empty());
} }
@ -1604,7 +1604,7 @@ bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS,
APInt NeededMask = DesiredMask & ~ActualMask; APInt NeededMask = DesiredMask & ~ActualMask;
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); CurDAG->computeKnownBits(LHS, KnownZero, KnownOne);
// If all the missing bits in the or are already known to be set, match! // If all the missing bits in the or are already known to be set, match!
if ((NeededMask & KnownOne) == NeededMask) if ((NeededMask & KnownOne) == NeededMask)

18
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -386,7 +386,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (Depth != 0) { if (Depth != 0) {
// If not at the root, Just compute the KnownZero/KnownOne bits to // If not at the root, Just compute the KnownZero/KnownOne bits to
// simplify things downstream. // simplify things downstream.
TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
return false; return false;
} }
// If this is the root being simplified, allow it to have multiple uses, // If this is the root being simplified, allow it to have multiple uses,
@ -416,7 +416,7 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
APInt LHSZero, LHSOne; APInt LHSZero, LHSOne;
// Do not increment Depth here; that can cause an infinite loop. // Do not increment Depth here; that can cause an infinite loop.
TLO.DAG.ComputeMaskedBits(Op.getOperand(0), LHSZero, LHSOne, Depth); TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth);
// If the LHS already has zeros where RHSC does, this and is dead. // If the LHS already has zeros where RHSC does, this and is dead.
if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask)) if ((LHSZero & NewMask) == (~RHSC->getAPIntValue() & NewMask))
return TLO.CombineTo(Op, Op.getOperand(0)); return TLO.CombineTo(Op, Op.getOperand(0));
@ -1065,8 +1065,8 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
} }
// FALL THROUGH // FALL THROUGH
default: default:
// Just use ComputeMaskedBits to compute output bits. // Just use computeKnownBits to compute output bits.
TLO.DAG.ComputeMaskedBits(Op, KnownZero, KnownOne, Depth); TLO.DAG.computeKnownBits(Op, KnownZero, KnownOne, Depth);
break; break;
} }
@ -1078,10 +1078,10 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
return false; return false;
} }
/// computeMaskedBitsForTargetNode - Determine which of the bits specified /// computeKnownBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the /// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets. /// KnownZero/KnownOne bitsets.
void TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, void TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,
@ -1111,7 +1111,7 @@ unsigned TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
} }
/// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly /// ValueHasExactlyOneBitSet - Test if the given value is known to have exactly
/// one bit set. This differs from ComputeMaskedBits in that it doesn't need to /// one bit set. This differs from computeKnownBits in that it doesn't need to
/// determine which bit is set. /// determine which bit is set.
/// ///
static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) { static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
@ -1134,11 +1134,11 @@ static bool ValueHasExactlyOneBitSet(SDValue Val, const SelectionDAG &DAG) {
// More could be done here, though the above checks are enough // More could be done here, though the above checks are enough
// to handle some common cases. // to handle some common cases.
// Fall back to ComputeMaskedBits to catch other known cases. // Fall back to computeKnownBits to catch other known cases.
EVT OpVT = Val.getValueType(); EVT OpVT = Val.getValueType();
unsigned BitWidth = OpVT.getScalarType().getSizeInBits(); unsigned BitWidth = OpVT.getScalarType().getSizeInBits();
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(Val, KnownZero, KnownOne); DAG.computeKnownBits(Val, KnownZero, KnownOne);
return (KnownZero.countPopulation() == BitWidth - 1) && return (KnownZero.countPopulation() == BitWidth - 1) &&
(KnownOne.countPopulation() == 1); (KnownOne.countPopulation() == 1);
} }

8
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -9520,7 +9520,7 @@ ARMTargetLowering::PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const {
if (Res.getNode()) { if (Res.getNode()) {
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(SDValue(N,0), KnownZero, KnownOne); DAG.computeKnownBits(SDValue(N,0), KnownZero, KnownOne);
// Capture demanded bits information that would be otherwise lost. // Capture demanded bits information that would be otherwise lost.
if (KnownZero == 0xfffffffe) if (KnownZero == 0xfffffffe)
Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res, Res = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Res,
@ -10107,7 +10107,7 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
return true; return true;
} }
void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, void ARMTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,
@ -10127,11 +10127,11 @@ void ARMTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
break; break;
case ARMISD::CMOV: { case ARMISD::CMOV: {
// Bits are known zero/one if known on the LHS and RHS. // Bits are known zero/one if known on the LHS and RHS.
DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1); DAG.computeKnownBits(Op.getOperand(0), KnownZero, KnownOne, Depth+1);
if (KnownZero == 0 && KnownOne == 0) return; if (KnownZero == 0 && KnownOne == 0) return;
APInt KnownZeroRHS, KnownOneRHS; APInt KnownZeroRHS, KnownOneRHS;
DAG.ComputeMaskedBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1); DAG.computeKnownBits(Op.getOperand(1), KnownZeroRHS, KnownOneRHS, Depth+1);
KnownZero &= KnownZeroRHS; KnownZero &= KnownZeroRHS;
KnownOne &= KnownOneRHS; KnownOne &= KnownOneRHS;
return; return;

2
lib/Target/ARM/ARMISelLowering.h
View File

@ -313,7 +313,7 @@ namespace llvm {
SDValue &Offset, ISD::MemIndexedMode &AM, SDValue &Offset, ISD::MemIndexedMode &AM,
SelectionDAG &DAG) const override; SelectionDAG &DAG) const override;
void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,
unsigned Depth) const override; unsigned Depth) const override;

6
lib/Target/ARM64/ARM64ISelDAGToDAG.cpp
View File

@ -1731,14 +1731,14 @@ static bool isBitfieldPositioningOp(SelectionDAG *CurDAG, SDValue Op,
assert(BitWidth == 32 || BitWidth == 64); assert(BitWidth == 32 || BitWidth == 64);
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
CurDAG->ComputeMaskedBits(Op, KnownZero, KnownOne); CurDAG->computeKnownBits(Op, KnownZero, KnownOne);
// Non-zero in the sense that they're not provably zero, which is the key // Non-zero in the sense that they're not provably zero, which is the key
// point if we want to use this value // point if we want to use this value
uint64_t NonZeroBits = (~KnownZero).getZExtValue(); uint64_t NonZeroBits = (~KnownZero).getZExtValue();
// Discard a constant AND mask if present. It's safe because the node will // Discard a constant AND mask if present. It's safe because the node will
// already have been factored into the ComputeMaskedBits calculation above. // already have been factored into the computeKnownBits calculation above.
uint64_t AndImm; uint64_t AndImm;
if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) { if (isOpcWithIntImmediate(Op.getNode(), ISD::AND, AndImm)) {
assert((~APInt(BitWidth, AndImm) & ~KnownZero) == 0); assert((~APInt(BitWidth, AndImm) & ~KnownZero) == 0);
@ -1839,7 +1839,7 @@ static bool isBitfieldInsertOpFromOr(SDNode *N, unsigned &Opc, SDValue &Dst,
// AND with imm. Indeed, simplify-demanded-bits may have removed // AND with imm. Indeed, simplify-demanded-bits may have removed
// the AND instruction because it proves it was useless. // the AND instruction because it proves it was useless.
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
CurDAG->ComputeMaskedBits(OrOpd1Val, KnownZero, KnownOne); CurDAG->computeKnownBits(OrOpd1Val, KnownZero, KnownOne);
// Check if there is enough room for the second operand to appear // Check if there is enough room for the second operand to appear
// in the first one // in the first one

8
lib/Target/ARM64/ARM64ISelLowering.cpp
View File

@ -562,10 +562,10 @@ EVT ARM64TargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
return VT.changeVectorElementTypeToInteger(); return VT.changeVectorElementTypeToInteger();
} }
/// computeMaskedBitsForTargetNode - Determine which of the bits specified in /// computeKnownBitsForTargetNode - Determine which of the bits specified in
/// Mask are known to be either zero or one and return them in the /// Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets. /// KnownZero/KnownOne bitsets.
void ARM64TargetLowering::computeMaskedBitsForTargetNode( void ARM64TargetLowering::computeKnownBitsForTargetNode(
const SDValue Op, APInt &KnownZero, APInt &KnownOne, const SDValue Op, APInt &KnownZero, APInt &KnownOne,
const SelectionDAG &DAG, unsigned Depth) const { const SelectionDAG &DAG, unsigned Depth) const {
switch (Op.getOpcode()) { switch (Op.getOpcode()) {
@ -573,8 +573,8 @@ void ARM64TargetLowering::computeMaskedBitsForTargetNode(
break; break;
case ARM64ISD::CSEL: { case ARM64ISD::CSEL: {
APInt KnownZero2, KnownOne2; APInt KnownZero2, KnownOne2;
DAG.ComputeMaskedBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1); DAG.computeKnownBits(Op->getOperand(0), KnownZero, KnownOne, Depth + 1);
DAG.ComputeMaskedBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1); DAG.computeKnownBits(Op->getOperand(1), KnownZero2, KnownOne2, Depth + 1);
KnownZero &= KnownZero2; KnownZero &= KnownZero2;
KnownOne &= KnownOne2; KnownOne &= KnownOne2;
break; break;

4
lib/Target/ARM64/ARM64ISelLowering.h
View File

@ -201,10 +201,10 @@ public:
/// value. /// value.
CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified in /// computeKnownBitsForTargetNode - Determine which of the bits specified in
/// Mask are known to be either zero or one and return them in the /// Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets. /// KnownZero/KnownOne bitsets.
void computeMaskedBitsForTargetNode(const SDValue Op, APInt &KnownZero, void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
APInt &KnownOne, const SelectionDAG &DAG, APInt &KnownOne, const SelectionDAG &DAG,
unsigned Depth = 0) const override; unsigned Depth = 0) const override;

6
lib/Target/PowerPC/PPCISelDAGToDAG.cpp
View File

@ -415,8 +415,8 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
SDLoc dl(N); SDLoc dl(N);
APInt LKZ, LKO, RKZ, RKO; APInt LKZ, LKO, RKZ, RKO;
CurDAG->ComputeMaskedBits(Op0, LKZ, LKO); CurDAG->computeKnownBits(Op0, LKZ, LKO);
CurDAG->ComputeMaskedBits(Op1, RKZ, RKO); CurDAG->computeKnownBits(Op1, RKZ, RKO);
unsigned TargetMask = LKZ.getZExtValue(); unsigned TargetMask = LKZ.getZExtValue();
unsigned InsertMask = RKZ.getZExtValue(); unsigned InsertMask = RKZ.getZExtValue();
@ -463,7 +463,7 @@ SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
// if we're going to fold the masking with the insert, all bits not // if we're going to fold the masking with the insert, all bits not
// know to be zero in the mask are known to be one. // know to be zero in the mask are known to be one.
APInt MKZ, MKO; APInt MKZ, MKO;
CurDAG->ComputeMaskedBits(Op1.getOperand(1), MKZ, MKO); CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
bool CanFoldMask = InsertMask == MKO.getZExtValue(); bool CanFoldMask = InsertMask == MKO.getZExtValue();
unsigned SHOpc = Op1.getOperand(0).getOpcode(); unsigned SHOpc = Op1.getOperand(0).getOpcode();

12
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1175,11 +1175,11 @@ bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
// disjoint. // disjoint.
APInt LHSKnownZero, LHSKnownOne; APInt LHSKnownZero, LHSKnownOne;
APInt RHSKnownZero, RHSKnownOne; APInt RHSKnownZero, RHSKnownOne;
DAG.ComputeMaskedBits(N.getOperand(0), DAG.computeKnownBits(N.getOperand(0),
LHSKnownZero, LHSKnownOne); LHSKnownZero, LHSKnownOne);
if (LHSKnownZero.getBoolValue()) { if (LHSKnownZero.getBoolValue()) {
DAG.ComputeMaskedBits(N.getOperand(1), DAG.computeKnownBits(N.getOperand(1),
RHSKnownZero, RHSKnownOne); RHSKnownZero, RHSKnownOne);
// If all of the bits are known zero on the LHS or RHS, the add won't // If all of the bits are known zero on the LHS or RHS, the add won't
// carry. // carry.
@ -1280,7 +1280,7 @@ bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
// (for better address arithmetic) if the LHS and RHS of the OR are // (for better address arithmetic) if the LHS and RHS of the OR are
// provably disjoint. // provably disjoint.
APInt LHSKnownZero, LHSKnownOne; APInt LHSKnownZero, LHSKnownOne;
DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne); DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) { if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
// If all of the bits are known zero on the LHS or RHS, the add won't // If all of the bits are known zero on the LHS or RHS, the add won't
@ -7355,8 +7355,8 @@ SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
// that the high bits are equal. // that the high bits are equal.
APInt Op1Zero, Op1One; APInt Op1Zero, Op1One;
APInt Op2Zero, Op2One; APInt Op2Zero, Op2One;
DAG.ComputeMaskedBits(N->getOperand(0), Op1Zero, Op1One); DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
DAG.ComputeMaskedBits(N->getOperand(1), Op2Zero, Op2One); DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
// We don't really care about what is known about the first bit (if // We don't really care about what is known about the first bit (if
// anything), so clear it in all masks prior to comparing them. // anything), so clear it in all masks prior to comparing them.
@ -8406,7 +8406,7 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
// Inline Assembly Support // Inline Assembly Support
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,

2
lib/Target/PowerPC/PPCISelLowering.h
View File

@ -400,7 +400,7 @@ namespace llvm {
unsigned getRegisterByName(const char* RegName, EVT VT) const override; unsigned getRegisterByName(const char* RegName, EVT VT) const override;
void computeMaskedBitsForTargetNode(const SDValue Op, void computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,

14
lib/Target/R600/AMDGPUISelLowering.cpp
View File

@ -1223,7 +1223,7 @@ SDValue AMDGPUTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
static bool isU24(SDValue Op, SelectionDAG &DAG) { static bool isU24(SDValue Op, SelectionDAG &DAG) {
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
EVT VT = Op.getValueType(); EVT VT = Op.getValueType();
DAG.ComputeMaskedBits(Op, KnownZero, KnownOne); DAG.computeKnownBits(Op, KnownZero, KnownOne);
return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24; return (VT.getSizeInBits() - KnownZero.countLeadingOnes()) <= 24;
} }
@ -1416,7 +1416,7 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const {
} }
} }
static void computeMaskedBitsForMinMax(const SDValue Op0, static void computeKnownBitsForMinMax(const SDValue Op0,
const SDValue Op1, const SDValue Op1,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
@ -1424,14 +1424,14 @@ static void computeMaskedBitsForMinMax(const SDValue Op0,
unsigned Depth) { unsigned Depth) {
APInt Op0Zero, Op0One; APInt Op0Zero, Op0One;
APInt Op1Zero, Op1One; APInt Op1Zero, Op1One;
DAG.ComputeMaskedBits(Op0, Op0Zero, Op0One, Depth); DAG.computeKnownBits(Op0, Op0Zero, Op0One, Depth);
DAG.ComputeMaskedBits(Op1, Op1Zero, Op1One, Depth); DAG.computeKnownBits(Op1, Op1Zero, Op1One, Depth);
KnownZero = Op0Zero & Op1Zero; KnownZero = Op0Zero & Op1Zero;
KnownOne = Op0One & Op1One; KnownOne = Op0One & Op1One;
} }
void AMDGPUTargetLowering::computeMaskedBitsForTargetNode( void AMDGPUTargetLowering::computeKnownBitsForTargetNode(
const SDValue Op, const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
@ -1448,7 +1448,7 @@ void AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
case AMDGPUIntrinsic::AMDGPU_umax: case AMDGPUIntrinsic::AMDGPU_umax:
case AMDGPUIntrinsic::AMDGPU_imin: case AMDGPUIntrinsic::AMDGPU_imin:
case AMDGPUIntrinsic::AMDGPU_umin: case AMDGPUIntrinsic::AMDGPU_umin:
computeMaskedBitsForMinMax(Op.getOperand(1), Op.getOperand(2), computeKnownBitsForMinMax(Op.getOperand(1), Op.getOperand(2),
KnownZero, KnownOne, DAG, Depth); KnownZero, KnownOne, DAG, Depth);
break; break;
default: default:
@ -1461,7 +1461,7 @@ void AMDGPUTargetLowering::computeMaskedBitsForTargetNode(
case AMDGPUISD::UMAX: case AMDGPUISD::UMAX:
case AMDGPUISD::SMIN: case AMDGPUISD::SMIN:
case AMDGPUISD::UMIN: case AMDGPUISD::UMIN:
computeMaskedBitsForMinMax(Op.getOperand(0), Op.getOperand(1), computeKnownBitsForMinMax(Op.getOperand(0), Op.getOperand(1),
KnownZero, KnownOne, DAG, Depth); KnownZero, KnownOne, DAG, Depth);
break; break;
default: default:

2
lib/Target/R600/AMDGPUISelLowering.h
View File

@ -118,7 +118,7 @@ public:
/// \brief Determine which of the bits specified in \p Mask are known to be /// \brief Determine which of the bits specified in \p Mask are known to be
/// either zero or one and return them in the \p KnownZero and \p KnownOne /// either zero or one and return them in the \p KnownZero and \p KnownOne
/// bitsets. /// bitsets.
void computeMaskedBitsForTargetNode(const SDValue Op, void computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,

6
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -1708,7 +1708,7 @@ EVT SparcTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
/// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to /// isMaskedValueZeroForTargetNode - Return true if 'Op & Mask' is known to
/// be zero. Op is expected to be a target specific node. Used by DAG /// be zero. Op is expected to be a target specific node. Used by DAG
/// combiner. /// combiner.
void SparcTargetLowering::computeMaskedBitsForTargetNode void SparcTargetLowering::computeKnownBitsForTargetNode
(const SDValue Op, (const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
@ -1722,8 +1722,8 @@ void SparcTargetLowering::computeMaskedBitsForTargetNode
case SPISD::SELECT_ICC: case SPISD::SELECT_ICC:
case SPISD::SELECT_XCC: case SPISD::SELECT_XCC:
case SPISD::SELECT_FCC: case SPISD::SELECT_FCC:
DAG.ComputeMaskedBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1); DAG.computeKnownBits(Op.getOperand(1), KnownZero, KnownOne, Depth+1);
DAG.ComputeMaskedBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1); DAG.computeKnownBits(Op.getOperand(0), KnownZero2, KnownOne2, Depth+1);
assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?"); assert((KnownZero & KnownOne) == 0 && "Bits known to be one AND zero?");
assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?"); assert((KnownZero2 & KnownOne2) == 0 && "Bits known to be one AND zero?");

4
lib/Target/Sparc/SparcISelLowering.h
View File

@ -57,10 +57,10 @@ namespace llvm {
SparcTargetLowering(TargetMachine &TM); SparcTargetLowering(TargetMachine &TM);
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified /// computeKnownBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the /// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets. /// KnownZero/KnownOne bitsets.
void computeMaskedBitsForTargetNode(const SDValue Op, void computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,

6
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp
View File

@ -665,7 +665,7 @@ bool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op,
uint64_t Used = allOnes(Op.getValueType().getSizeInBits()); uint64_t Used = allOnes(Op.getValueType().getSizeInBits());
if (Used != (AndMask | InsertMask)) { if (Used != (AndMask | InsertMask)) {
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
CurDAG->ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne); CurDAG->computeKnownBits(Op.getOperand(0), KnownZero, KnownOne);
if (Used != (AndMask | InsertMask | KnownZero.getZExtValue())) if (Used != (AndMask | InsertMask | KnownZero.getZExtValue()))
return false; return false;
} }
@ -714,7 +714,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
// been removed from the mask. See if adding them back in makes the // been removed from the mask. See if adding them back in makes the
// mask suitable. // mask suitable.
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne); CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
Mask |= KnownZero.getZExtValue(); Mask |= KnownZero.getZExtValue();
if (!refineRxSBGMask(RxSBG, Mask)) if (!refineRxSBGMask(RxSBG, Mask))
return false; return false;
@ -738,7 +738,7 @@ bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) const {
// been removed from the mask. See if adding them back in makes the // been removed from the mask. See if adding them back in makes the
// mask suitable. // mask suitable.
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne); CurDAG->computeKnownBits(Input, KnownZero, KnownOne);
Mask &= ~KnownOne.getZExtValue(); Mask &= ~KnownOne.getZExtValue();
if (!refineRxSBGMask(RxSBG, Mask)) if (!refineRxSBGMask(RxSBG, Mask))
return false; return false;

4
lib/Target/SystemZ/SystemZISelLowering.cpp
View File

@ -2125,8 +2125,8 @@ SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
// Get the known-zero masks for each operand. // Get the known-zero masks for each operand.
SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) }; SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
APInt KnownZero[2], KnownOne[2]; APInt KnownZero[2], KnownOne[2];
DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]); DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]); DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
// See if the upper 32 bits of one operand and the lower 32 bits of the // See if the upper 32 bits of one operand and the lower 32 bits of the
// other are known zero. They are the low and high operands respectively. // other are known zero. They are the low and high operands respectively.

2
lib/Target/X86/X86ISelDAGToDAG.cpp
View File

@ -927,7 +927,7 @@ static bool FoldMaskAndShiftToScale(SelectionDAG &DAG, SDValue N,
APInt MaskedHighBits = APInt MaskedHighBits =
APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ); APInt::getHighBitsSet(X.getSimpleValueType().getSizeInBits(), MaskLZ);
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(X, KnownZero, KnownOne); DAG.computeKnownBits(X, KnownZero, KnownOne);
if (MaskedHighBits != KnownZero) return true; if (MaskedHighBits != KnownZero) return true;
// We've identified a pattern that can be transformed into a single shift // We've identified a pattern that can be transformed into a single shift

6
lib/Target/X86/X86ISelLowering.cpp
View File

@ -10217,7 +10217,7 @@ SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC,
unsigned AndBitWidth = And.getValueSizeInBits(); unsigned AndBitWidth = And.getValueSizeInBits();
if (BitWidth > AndBitWidth) { if (BitWidth > AndBitWidth) {
APInt Zeros, Ones; APInt Zeros, Ones;
DAG.ComputeMaskedBits(Op0, Zeros, Ones); DAG.computeKnownBits(Op0, Zeros, Ones);
if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth)
return SDValue(); return SDValue();
} }
@ -17103,7 +17103,7 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
// X86 Optimization Hooks // X86 Optimization Hooks
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, void X86TargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,
@ -17973,7 +17973,7 @@ static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG,
// Another special case: If C was a sign bit, the sub has been // Another special case: If C was a sign bit, the sub has been
// canonicalized into a xor. // canonicalized into a xor.
// FIXME: Would it be better to use ComputeMaskedBits to determine whether // FIXME: Would it be better to use computeKnownBits to determine whether
// it's safe to decanonicalize the xor? // it's safe to decanonicalize the xor?
// x s< 0 ? x^C : 0 --> subus x, C // x s< 0 ? x^C : 0 --> subus x, C
if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR && if (CC == ISD::SETLT && Other->getOpcode() == ISD::XOR &&

4
lib/Target/X86/X86ISelLowering.h
View File

@ -618,10 +618,10 @@ namespace llvm {
/// getSetCCResultType - Return the value type to use for ISD::SETCC. /// getSetCCResultType - Return the value type to use for ISD::SETCC.
EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override; EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
/// computeMaskedBitsForTargetNode - Determine which of the bits specified /// computeKnownBitsForTargetNode - Determine which of the bits specified
/// in Mask are known to be either zero or one and return them in the /// in Mask are known to be either zero or one and return them in the
/// KnownZero/KnownOne bitsets. /// KnownZero/KnownOne bitsets.
void computeMaskedBitsForTargetNode(const SDValue Op, void computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,

4
lib/Target/X86/X86InstrCompiler.td
View File

@ -1187,9 +1187,9 @@ def or_is_add : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue()); return CurDAG->MaskedValueIsZero(N->getOperand(0), CN->getAPIntValue());
APInt KnownZero0, KnownOne0; APInt KnownZero0, KnownOne0;
CurDAG->ComputeMaskedBits(N->getOperand(0), KnownZero0, KnownOne0, 0); CurDAG->computeKnownBits(N->getOperand(0), KnownZero0, KnownOne0, 0);
APInt KnownZero1, KnownOne1; APInt KnownZero1, KnownOne1;
CurDAG->ComputeMaskedBits(N->getOperand(1), KnownZero1, KnownOne1, 0); CurDAG->computeKnownBits(N->getOperand(1), KnownZero1, KnownOne1, 0);
return (~KnownZero0 & ~KnownZero1) == 0; return (~KnownZero0 & ~KnownZero1) == 0;
}]>; }]>;

10
lib/Target/XCore/XCoreISelLowering.cpp
View File

@ -434,7 +434,7 @@ lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base,
static bool isWordAligned(SDValue Value, SelectionDAG &DAG) static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
{ {
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
DAG.ComputeMaskedBits(Value, KnownZero, KnownOne); DAG.computeKnownBits(Value, KnownZero, KnownOne);
return KnownZero.countTrailingOnes() >= 2; return KnownZero.countTrailingOnes() >= 2;
} }
@ -1699,7 +1699,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
VT.getSizeInBits() - 1); VT.getSizeInBits() - 1);
DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); DAG.computeKnownBits(N2, KnownZero, KnownOne);
if ((KnownZero & Mask) == Mask) { if ((KnownZero & Mask) == Mask) {
SDValue Carry = DAG.getConstant(0, VT); SDValue Carry = DAG.getConstant(0, VT);
SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
@ -1722,7 +1722,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
VT.getSizeInBits() - 1); VT.getSizeInBits() - 1);
DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); DAG.computeKnownBits(N2, KnownZero, KnownOne);
if ((KnownZero & Mask) == Mask) { if ((KnownZero & Mask) == Mask) {
SDValue Borrow = N2; SDValue Borrow = N2;
SDValue Result = DAG.getNode(ISD::SUB, dl, VT, SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
@ -1738,7 +1738,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
APInt KnownZero, KnownOne; APInt KnownZero, KnownOne;
APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(), APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
VT.getSizeInBits() - 1); VT.getSizeInBits() - 1);
DAG.ComputeMaskedBits(N2, KnownZero, KnownOne); DAG.computeKnownBits(N2, KnownZero, KnownOne);
if ((KnownZero & Mask) == Mask) { if ((KnownZero & Mask) == Mask) {
SDValue Borrow = DAG.getConstant(0, VT); SDValue Borrow = DAG.getConstant(0, VT);
SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2); SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
@ -1860,7 +1860,7 @@ SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
return SDValue(); return SDValue();
} }
void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,

2
lib/Target/XCore/XCoreISelLowering.h
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@ -183,7 +183,7 @@ namespace llvm {
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override; SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
void computeMaskedBitsForTargetNode(const SDValue Op, void computeKnownBitsForTargetNode(const SDValue Op,
APInt &KnownZero, APInt &KnownZero,
APInt &KnownOne, APInt &KnownOne,
const SelectionDAG &DAG, const SelectionDAG &DAG,

4
lib/Transforms/InstCombine/InstCombine.h
View File

@ -313,9 +313,9 @@ public:
return nullptr; // Don't do anything with FI return nullptr; // Don't do anything with FI
} }
void ComputeMaskedBits(Value *V, APInt &KnownZero, APInt &KnownOne, void computeKnownBits(Value *V, APInt &KnownZero, APInt &KnownOne,
unsigned Depth = 0) const { unsigned Depth = 0) const {
return llvm::ComputeMaskedBits(V, KnownZero, KnownOne, DL, Depth); return llvm::computeKnownBits(V, KnownZero, KnownOne, DL, Depth);
} }
bool MaskedValueIsZero(Value *V, const APInt &Mask, bool MaskedValueIsZero(Value *V, const APInt &Mask,

6
lib/Transforms/InstCombine/InstCombineAddSub.cpp
View File

@ -979,7 +979,7 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
IntegerType *IT = cast<IntegerType>(I.getType()); IntegerType *IT = cast<IntegerType>(I.getType());
APInt LHSKnownOne(IT->getBitWidth(), 0); APInt LHSKnownOne(IT->getBitWidth(), 0);
APInt LHSKnownZero(IT->getBitWidth(), 0); APInt LHSKnownZero(IT->getBitWidth(), 0);
ComputeMaskedBits(XorLHS, LHSKnownZero, LHSKnownOne); computeKnownBits(XorLHS, LHSKnownZero, LHSKnownOne);
if ((XorRHS->getValue() | LHSKnownZero).isAllOnesValue()) if ((XorRHS->getValue() | LHSKnownZero).isAllOnesValue())
return BinaryOperator::CreateSub(ConstantExpr::getAdd(XorRHS, CI), return BinaryOperator::CreateSub(ConstantExpr::getAdd(XorRHS, CI),
XorLHS); XorLHS);
@ -1047,11 +1047,11 @@ Instruction *InstCombiner::visitAdd(BinaryOperator &I) {
if (IntegerType *IT = dyn_cast<IntegerType>(I.getType())) { if (IntegerType *IT = dyn_cast<IntegerType>(I.getType())) {
APInt LHSKnownOne(IT->getBitWidth(), 0); APInt LHSKnownOne(IT->getBitWidth(), 0);
APInt LHSKnownZero(IT->getBitWidth(), 0); APInt LHSKnownZero(IT->getBitWidth(), 0);
ComputeMaskedBits(LHS, LHSKnownZero, LHSKnownOne); computeKnownBits(LHS, LHSKnownZero, LHSKnownOne);
if (LHSKnownZero != 0) { if (LHSKnownZero != 0) {
APInt RHSKnownOne(IT->getBitWidth(), 0); APInt RHSKnownOne(IT->getBitWidth(), 0);
APInt RHSKnownZero(IT->getBitWidth(), 0); APInt RHSKnownZero(IT->getBitWidth(), 0);
ComputeMaskedBits(RHS, RHSKnownZero, RHSKnownOne); computeKnownBits(RHS, RHSKnownZero, RHSKnownOne);
// No bits in common -> bitwise or. // No bits in common -> bitwise or.
if ((LHSKnownZero|RHSKnownZero).isAllOnesValue()) if ((LHSKnownZero|RHSKnownZero).isAllOnesValue())

12
lib/Transforms/InstCombine/InstCombineCalls.cpp
View File

@ -322,7 +322,7 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
uint32_t BitWidth = IT->getBitWidth(); uint32_t BitWidth = IT->getBitWidth();
APInt KnownZero(BitWidth, 0); APInt KnownZero(BitWidth, 0);
APInt KnownOne(BitWidth, 0); APInt KnownOne(BitWidth, 0);
ComputeMaskedBits(II->getArgOperand(0), KnownZero, KnownOne); computeKnownBits(II->getArgOperand(0), KnownZero, KnownOne);
unsigned TrailingZeros = KnownOne.countTrailingZeros(); unsigned TrailingZeros = KnownOne.countTrailingZeros();
APInt Mask(APInt::getLowBitsSet(BitWidth, TrailingZeros)); APInt Mask(APInt::getLowBitsSet(BitWidth, TrailingZeros));
if ((Mask & KnownZero) == Mask) if ((Mask & KnownZero) == Mask)
@ -340,7 +340,7 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
uint32_t BitWidth = IT->getBitWidth(); uint32_t BitWidth = IT->getBitWidth();
APInt KnownZero(BitWidth, 0); APInt KnownZero(BitWidth, 0);
APInt KnownOne(BitWidth, 0); APInt KnownOne(BitWidth, 0);
ComputeMaskedBits(II->getArgOperand(0), KnownZero, KnownOne); computeKnownBits(II->getArgOperand(0), KnownZero, KnownOne);
unsigned LeadingZeros = KnownOne.countLeadingZeros(); unsigned LeadingZeros = KnownOne.countLeadingZeros();
APInt Mask(APInt::getHighBitsSet(BitWidth, LeadingZeros)); APInt Mask(APInt::getHighBitsSet(BitWidth, LeadingZeros));
if ((Mask & KnownZero) == Mask) if ((Mask & KnownZero) == Mask)
@ -355,14 +355,14 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
uint32_t BitWidth = IT->getBitWidth(); uint32_t BitWidth = IT->getBitWidth();
APInt LHSKnownZero(BitWidth, 0); APInt LHSKnownZero(BitWidth, 0);
APInt LHSKnownOne(BitWidth, 0); APInt LHSKnownOne(BitWidth, 0);
ComputeMaskedBits(LHS, LHSKnownZero, LHSKnownOne); computeKnownBits(LHS, LHSKnownZero, LHSKnownOne);
bool LHSKnownNegative = LHSKnownOne[BitWidth - 1]; bool LHSKnownNegative = LHSKnownOne[BitWidth - 1];
bool LHSKnownPositive = LHSKnownZero[BitWidth - 1]; bool LHSKnownPositive = LHSKnownZero[BitWidth - 1];
if (LHSKnownNegative || LHSKnownPositive) { if (LHSKnownNegative || LHSKnownPositive) {
APInt RHSKnownZero(BitWidth, 0); APInt RHSKnownZero(BitWidth, 0);
APInt RHSKnownOne(BitWidth, 0); APInt RHSKnownOne(BitWidth, 0);
ComputeMaskedBits(RHS, RHSKnownZero, RHSKnownOne); computeKnownBits(RHS, RHSKnownZero, RHSKnownOne);
bool RHSKnownNegative = RHSKnownOne[BitWidth - 1]; bool RHSKnownNegative = RHSKnownOne[BitWidth - 1];
bool RHSKnownPositive = RHSKnownZero[BitWidth - 1]; bool RHSKnownPositive = RHSKnownZero[BitWidth - 1];
if (LHSKnownNegative && RHSKnownNegative) { if (LHSKnownNegative && RHSKnownNegative) {
@ -449,10 +449,10 @@ Instruction *InstCombiner::visitCallInst(CallInst &CI) {
APInt LHSKnownZero(BitWidth, 0); APInt LHSKnownZero(BitWidth, 0);
APInt LHSKnownOne(BitWidth, 0); APInt LHSKnownOne(BitWidth, 0);
ComputeMaskedBits(LHS, LHSKnownZero, LHSKnownOne); computeKnownBits(LHS, LHSKnownZero, LHSKnownOne);
APInt RHSKnownZero(BitWidth, 0); APInt RHSKnownZero(BitWidth, 0);
APInt RHSKnownOne(BitWidth, 0); APInt RHSKnownOne(BitWidth, 0);
ComputeMaskedBits(RHS, RHSKnownZero, RHSKnownOne); computeKnownBits(RHS, RHSKnownZero, RHSKnownOne);
// Get the largest possible values for each operand. // Get the largest possible values for each operand.
APInt LHSMax = ~LHSKnownZero; APInt LHSMax = ~LHSKnownZero;

8
lib/Transforms/InstCombine/InstCombineCasts.cpp
View File

@ -553,7 +553,7 @@ Instruction *InstCombiner::transformZExtICmp(ICmpInst *ICI, Instruction &CI,
// If Op1C some other power of two, convert: // If Op1C some other power of two, convert:
uint32_t BitWidth = Op1C->getType()->getBitWidth(); uint32_t BitWidth = Op1C->getType()->getBitWidth();
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(ICI->getOperand(0), KnownZero, KnownOne); computeKnownBits(ICI->getOperand(0), KnownZero, KnownOne);
APInt KnownZeroMask(~KnownZero); APInt KnownZeroMask(~KnownZero);
if (KnownZeroMask.isPowerOf2()) { // Exactly 1 possible 1? if (KnownZeroMask.isPowerOf2()) { // Exactly 1 possible 1?
@ -601,8 +601,8 @@ Instruction *InstCombiner::transformZExtICmp(ICmpInst *ICI, Instruction &CI,
APInt KnownZeroLHS(BitWidth, 0), KnownOneLHS(BitWidth, 0); APInt KnownZeroLHS(BitWidth, 0), KnownOneLHS(BitWidth, 0);
APInt KnownZeroRHS(BitWidth, 0), KnownOneRHS(BitWidth, 0); APInt KnownZeroRHS(BitWidth, 0), KnownOneRHS(BitWidth, 0);
ComputeMaskedBits(LHS, KnownZeroLHS, KnownOneLHS); computeKnownBits(LHS, KnownZeroLHS, KnownOneLHS);
ComputeMaskedBits(RHS, KnownZeroRHS, KnownOneRHS); computeKnownBits(RHS, KnownZeroRHS, KnownOneRHS);
if (KnownZeroLHS == KnownZeroRHS && KnownOneLHS == KnownOneRHS) { if (KnownZeroLHS == KnownZeroRHS && KnownOneLHS == KnownOneRHS) {
APInt KnownBits = KnownZeroLHS | KnownOneLHS; APInt KnownBits = KnownZeroLHS | KnownOneLHS;
@ -921,7 +921,7 @@ Instruction *InstCombiner::transformSExtICmp(ICmpInst *ICI, Instruction &CI) {
ICI->isEquality() && (Op1C->isZero() || Op1C->getValue().isPowerOf2())){ ICI->isEquality() && (Op1C->isZero() || Op1C->getValue().isPowerOf2())){
unsigned BitWidth = Op1C->getType()->getBitWidth(); unsigned BitWidth = Op1C->getType()->getBitWidth();
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(Op0, KnownZero, KnownOne); computeKnownBits(Op0, KnownZero, KnownOne);
APInt KnownZeroMask(~KnownZero); APInt KnownZeroMask(~KnownZero);
if (KnownZeroMask.isPowerOf2()) { if (KnownZeroMask.isPowerOf2()) {

2
lib/Transforms/InstCombine/InstCombineCompares.cpp
View File

@ -1058,7 +1058,7 @@ Instruction *InstCombiner::visitICmpInstWithInstAndIntCst(ICmpInst &ICI,
unsigned DstBits = LHSI->getType()->getPrimitiveSizeInBits(), unsigned DstBits = LHSI->getType()->getPrimitiveSizeInBits(),
SrcBits = LHSI->getOperand(0)->getType()->getPrimitiveSizeInBits(); SrcBits = LHSI->getOperand(0)->getType()->getPrimitiveSizeInBits();
APInt KnownZero(SrcBits, 0), KnownOne(SrcBits, 0); APInt KnownZero(SrcBits, 0), KnownOne(SrcBits, 0);
ComputeMaskedBits(LHSI->getOperand(0), KnownZero, KnownOne); computeKnownBits(LHSI->getOperand(0), KnownZero, KnownOne);
// If all the high bits are known, we can do this xform. // If all the high bits are known, we can do this xform.
if ((KnownZero|KnownOne).countLeadingOnes() >= SrcBits-DstBits) { if ((KnownZero|KnownOne).countLeadingOnes() >= SrcBits-DstBits) {

26
lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
View File

@ -144,7 +144,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
Instruction *I = dyn_cast<Instruction>(V); Instruction *I = dyn_cast<Instruction>(V);
if (!I) { if (!I) {
ComputeMaskedBits(V, KnownZero, KnownOne, Depth); computeKnownBits(V, KnownZero, KnownOne, Depth);
return nullptr; // Only analyze instructions. return nullptr; // Only analyze instructions.
} }
@ -158,8 +158,8 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// this instruction has a simpler value in that context. // this instruction has a simpler value in that context.
if (I->getOpcode() == Instruction::And) { if (I->getOpcode() == Instruction::And) {
// If either the LHS or the RHS are Zero, the result is zero. // If either the LHS or the RHS are Zero, the result is zero.
ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1); computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1);
ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
// If all of the demanded bits are known 1 on one side, return the other. // If all of the demanded bits are known 1 on one side, return the other.
// These bits cannot contribute to the result of the 'and' in this // These bits cannot contribute to the result of the 'and' in this
@ -180,8 +180,8 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// only bits from X or Y are demanded. // only bits from X or Y are demanded.
// If either the LHS or the RHS are One, the result is One. // If either the LHS or the RHS are One, the result is One.
ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1); computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1);
ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
// If all of the demanded bits are known zero on one side, return the // If all of the demanded bits are known zero on one side, return the
// other. These bits cannot contribute to the result of the 'or' in this // other. These bits cannot contribute to the result of the 'or' in this
@ -205,8 +205,8 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// We can simplify (X^Y) -> X or Y in the user's context if we know that // We can simplify (X^Y) -> X or Y in the user's context if we know that
// only bits from X or Y are demanded. // only bits from X or Y are demanded.
ComputeMaskedBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1); computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth+1);
ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
// If all of the demanded bits are known zero on one side, return the // If all of the demanded bits are known zero on one side, return the
// other. // other.
@ -217,7 +217,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
} }
// Compute the KnownZero/KnownOne bits to simplify things downstream. // Compute the KnownZero/KnownOne bits to simplify things downstream.
ComputeMaskedBits(I, KnownZero, KnownOne, Depth); computeKnownBits(I, KnownZero, KnownOne, Depth);
return nullptr; return nullptr;
} }
@ -230,7 +230,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
switch (I->getOpcode()) { switch (I->getOpcode()) {
default: default:
ComputeMaskedBits(I, KnownZero, KnownOne, Depth); computeKnownBits(I, KnownZero, KnownOne, Depth);
break; break;
case Instruction::And: case Instruction::And:
// If either the LHS or the RHS are Zero, the result is zero. // If either the LHS or the RHS are Zero, the result is zero.
@ -579,9 +579,9 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
return I; return I;
} }
// Otherwise just hand the sub off to ComputeMaskedBits to fill in // Otherwise just hand the sub off to computeKnownBits to fill in
// the known zeros and ones. // the known zeros and ones.
ComputeMaskedBits(V, KnownZero, KnownOne, Depth); computeKnownBits(V, KnownZero, KnownOne, Depth);
// Turn this into a xor if LHS is 2^n-1 and the remaining bits are known // Turn this into a xor if LHS is 2^n-1 and the remaining bits are known
// zero. // zero.
@ -752,7 +752,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
// remainder is zero. // remainder is zero.
if (DemandedMask.isNegative() && KnownZero.isNonNegative()) { if (DemandedMask.isNegative() && KnownZero.isNonNegative()) {
APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0); APInt LHSKnownZero(BitWidth, 0), LHSKnownOne(BitWidth, 0);
ComputeMaskedBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1); computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth+1);
// If it's known zero, our sign bit is also zero. // If it's known zero, our sign bit is also zero.
if (LHSKnownZero.isNegative()) if (LHSKnownZero.isNegative())
KnownZero.setBit(KnownZero.getBitWidth() - 1); KnownZero.setBit(KnownZero.getBitWidth() - 1);
@ -814,7 +814,7 @@ Value *InstCombiner::SimplifyDemandedUseBits(Value *V, APInt DemandedMask,
return nullptr; return nullptr;
} }
} }
ComputeMaskedBits(V, KnownZero, KnownOne, Depth); computeKnownBits(V, KnownZero, KnownOne, Depth);
break; break;
} }

2
lib/Transforms/Scalar/SeparateConstOffsetFromGEP.cpp
View File

@ -393,7 +393,7 @@ void ConstantOffsetExtractor::ComputeKnownBits(Value *V, APInt &KnownOne,
IntegerType *IT = cast<IntegerType>(V->getType()); IntegerType *IT = cast<IntegerType>(V->getType());
KnownOne = APInt(IT->getBitWidth(), 0); KnownOne = APInt(IT->getBitWidth(), 0);
KnownZero = APInt(IT->getBitWidth(), 0); KnownZero = APInt(IT->getBitWidth(), 0);
llvm::ComputeMaskedBits(V, KnownZero, KnownOne, DL, 0); llvm::computeKnownBits(V, KnownZero, KnownOne, DL, 0);
} }
bool ConstantOffsetExtractor::NoCommonBits(Value *LHS, Value *RHS) const { bool ConstantOffsetExtractor::NoCommonBits(Value *LHS, Value *RHS) const {

2
lib/Transforms/Utils/Local.cpp
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@ -932,7 +932,7 @@ unsigned llvm::getOrEnforceKnownAlignment(Value *V, unsigned PrefAlign,
unsigned BitWidth = DL ? DL->getPointerTypeSizeInBits(V->getType()) : 64; unsigned BitWidth = DL ? DL->getPointerTypeSizeInBits(V->getType()) : 64;
APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0); APInt KnownZero(BitWidth, 0), KnownOne(BitWidth, 0);
ComputeMaskedBits(V, KnownZero, KnownOne, DL); computeKnownBits(V, KnownZero, KnownOne, DL);
unsigned TrailZ = KnownZero.countTrailingOnes(); unsigned TrailZ = KnownZero.countTrailingOnes();
// Avoid trouble with ridiculously large TrailZ values, such as // Avoid trouble with ridiculously large TrailZ values, such as

2
lib/Transforms/Utils/SimplifyCFG.cpp
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@ -3190,7 +3190,7 @@ static bool EliminateDeadSwitchCases(SwitchInst *SI) {
Value *Cond = SI->getCondition(); Value *Cond = SI->getCondition();
unsigned Bits = Cond->getType()->getIntegerBitWidth(); unsigned Bits = Cond->getType()->getIntegerBitWidth();
APInt KnownZero(Bits, 0), KnownOne(Bits, 0); APInt KnownZero(Bits, 0), KnownOne(Bits, 0);
ComputeMaskedBits(Cond, KnownZero, KnownOne); computeKnownBits(Cond, KnownZero, KnownOne);
// Gather dead cases. // Gather dead cases.
SmallVector<ConstantInt*, 8> DeadCases; SmallVector<ConstantInt*, 8> DeadCases;

2
test/CodeGen/ARM/zextload_demandedbits.ll
View File

@ -6,7 +6,7 @@ target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:64-
%struct.spam = type { [3 x i32] } %struct.spam = type { [3 x i32] }
%struct.barney = type { [2 x i32], [2 x i32] } %struct.barney = type { [2 x i32], [2 x i32] }
; Make sure that the sext op does not get lost due to ComputeMaskedBits. ; Make sure that the sext op does not get lost due to computeKnownBits.
; CHECK: quux ; CHECK: quux
; CHECK: lsl ; CHECK: lsl
; CHECK: asr ; CHECK: asr

2
test/CodeGen/R600/sext-in-reg.ll
View File

@ -363,7 +363,7 @@ define void @vgpr_sext_in_reg_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x
} }
; FIXME: The BFE should really be eliminated. I think it should happen ; FIXME: The BFE should really be eliminated. I think it should happen
; when computeMaskedBitsForTargetNode is implemented for imax. ; when computeKnownBitsForTargetNode is implemented for imax.
; FUNC-LABEL: @sext_in_reg_to_illegal_type ; FUNC-LABEL: @sext_in_reg_to_illegal_type
; SI: BUFFER_LOAD_SBYTE ; SI: BUFFER_LOAD_SBYTE

2
test/CodeGen/X86/live-out-reg-info.ll
View File

@ -1,7 +1,7 @@
; RUN: llc < %s -march=x86-64 | grep testb ; RUN: llc < %s -march=x86-64 | grep testb
; Make sure dagcombine doesn't eliminate the comparison due ; Make sure dagcombine doesn't eliminate the comparison due
; to an off-by-one bug with ComputeMaskedBits information. ; to an off-by-one bug with computeKnownBits information.
declare void @qux() declare void @qux()