mirror of
https://github.com/c64scene-ar/llvm-6502.git
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Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@200626 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper
parent
3c53b6f1ec
commit
6b6dfa5c5a
@ -310,12 +310,15 @@ namespace X86II {
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//===------------------------------------------------------------------===//
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// Actual flags...
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// OpSize - Set if this instruction requires an operand size prefix (0x66),
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// which most often indicates that the instruction operates on 16 bit data
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// instead of 32 bit data. OpSize16 in 16 bit mode indicates that the
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// instruction operates on 32 bit data instead of 16 bit data.
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OpSize = 1 << 6,
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OpSize16 = 1 << 7,
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// OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
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// OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
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// 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
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// prefix in 16-bit mode.
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OpSizeShift = 6,
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OpSizeMask = 0x3 << OpSizeShift,
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OpSize16 = 1,
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OpSize32 = 2,
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// AsSize - Set if this instruction requires an operand size prefix (0x67),
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// which most often indicates that the instruction address 16 bit address
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@ -1119,7 +1119,8 @@ void X86MCCodeEmitter::EmitOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
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raw_ostream &OS) const {
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// Emit the operand size opcode prefix as needed.
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if (TSFlags & (is16BitMode(STI) ? X86II::OpSize16 : X86II::OpSize))
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unsigned char OpSize = (TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift;
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if (OpSize == (is16BitMode(STI) ? X86II::OpSize32 : X86II::OpSize16))
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EmitByte(0x66, CurByte, OS);
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switch (TSFlags & X86II::OpPrefixMask) {
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@ -1277,7 +1278,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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// Emit segment override opcode prefix as needed (not for %ds).
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if (MI.getOperand(2).getReg() != X86::DS)
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EmitSegmentOverridePrefix(CurByte, 2, MI, OS);
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// Emit OpSize prefix as needed.
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// Emit AdSize prefix as needed.
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if ((!is32BitMode(STI) && siReg == X86::ESI) ||
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(is32BitMode(STI) && siReg == X86::SI))
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EmitByte(0x67, CurByte, OS);
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@ -1290,7 +1291,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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// Emit segment override opcode prefix as needed (not for %ds).
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if (MI.getOperand(1).getReg() != X86::DS)
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EmitSegmentOverridePrefix(CurByte, 1, MI, OS);
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// Emit OpSize prefix as needed.
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// Emit AdSize prefix as needed.
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if ((!is32BitMode(STI) && siReg == X86::ESI) ||
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(is32BitMode(STI) && siReg == X86::SI))
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EmitByte(0x67, CurByte, OS);
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@ -1300,7 +1301,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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}
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case X86II::RawFrmDst: {
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unsigned siReg = MI.getOperand(0).getReg();
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// Emit OpSize prefix as needed.
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// Emit AdSize prefix as needed.
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if ((!is32BitMode(STI) && siReg == X86::EDI) ||
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(is32BitMode(STI) && siReg == X86::DI))
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EmitByte(0x67, CurByte, OS);
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@ -655,7 +655,7 @@ void Emitter<CodeEmitter>::emitOpcodePrefix(uint64_t TSFlags,
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const MachineInstr &MI,
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const MCInstrDesc *Desc) const {
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// Emit the operand size opcode prefix as needed.
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if (TSFlags & X86II::OpSize)
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if (((TSFlags & X86II::OpSizeMask) >> X86II::OpSizeShift) == X86II::OpSize16)
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MCE.emitByte(0x66);
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switch (Desc->TSFlags & X86II::OpPrefixMask) {
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@ -18,19 +18,19 @@ let SchedRW = [WriteLEA] in {
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let neverHasSideEffects = 1 in
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def LEA16r : I<0x8D, MRMSrcMem,
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(outs GR16:$dst), (ins i32mem:$src),
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"lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize;
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"lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize16;
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let isReMaterializable = 1 in
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def LEA32r : I<0x8D, MRMSrcMem,
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(outs GR32:$dst), (ins i32mem:$src),
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"lea{l}\t{$src|$dst}, {$dst|$src}",
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[(set GR32:$dst, lea32addr:$src)], IIC_LEA>,
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OpSize16, Requires<[Not64BitMode]>;
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OpSize32, Requires<[Not64BitMode]>;
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def LEA64_32r : I<0x8D, MRMSrcMem,
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(outs GR32:$dst), (ins lea64_32mem:$src),
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"lea{l}\t{$src|$dst}, {$dst|$src}",
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[(set GR32:$dst, lea64_32addr:$src)], IIC_LEA>,
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OpSize16, Requires<[In64BitMode]>;
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OpSize32, Requires<[In64BitMode]>;
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let isReMaterializable = 1 in
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def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins lea64mem:$src),
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@ -68,13 +68,13 @@ def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src",
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let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in
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def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src),
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"mul{w}\t$src",
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[], IIC_MUL16_REG>, OpSize, Sched<[WriteIMul]>;
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[], IIC_MUL16_REG>, OpSize16, Sched<[WriteIMul]>;
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// EAX,EDX = EAX*GR32
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in
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def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src),
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"mul{l}\t$src",
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[/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/],
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IIC_MUL32_REG>, OpSize16, Sched<[WriteIMul]>;
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IIC_MUL32_REG>, OpSize32, Sched<[WriteIMul]>;
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// RAX,RDX = RAX*GR64
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in
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def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src),
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@ -95,12 +95,12 @@ let mayLoad = 1, neverHasSideEffects = 1 in {
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
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"mul{w}\t$src",
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[], IIC_MUL16_MEM>, OpSize, SchedLoadReg<WriteIMulLd>;
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[], IIC_MUL16_MEM>, OpSize16, SchedLoadReg<WriteIMulLd>;
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// EAX,EDX = EAX*[mem32]
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src),
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"mul{l}\t$src",
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[], IIC_MUL32_MEM>, OpSize16, SchedLoadReg<WriteIMulLd>;
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[], IIC_MUL32_MEM>, OpSize32, SchedLoadReg<WriteIMulLd>;
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// RAX,RDX = RAX*[mem64]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src),
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@ -115,11 +115,11 @@ def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [],
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// AX,DX = AX*GR16
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [],
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IIC_IMUL16_RR>, OpSize, Sched<[WriteIMul]>;
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IIC_IMUL16_RR>, OpSize16, Sched<[WriteIMul]>;
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// EAX,EDX = EAX*GR32
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [],
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IIC_IMUL32_RR>, OpSize16, Sched<[WriteIMul]>;
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IIC_IMUL32_RR>, OpSize32, Sched<[WriteIMul]>;
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// RAX,RDX = RAX*GR64
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [],
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@ -133,12 +133,12 @@ def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src),
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// AX,DX = AX*[mem16]
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let Defs = [AX,DX,EFLAGS], Uses = [AX] in
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def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src),
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"imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize,
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"imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize16,
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SchedLoadReg<WriteIMulLd>;
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// EAX,EDX = EAX*[mem32]
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in
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def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src),
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"imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize16,
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"imul{l}\t$src", [], IIC_IMUL32_MEM>, OpSize32,
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SchedLoadReg<WriteIMulLd>;
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// RAX,RDX = RAX*[mem64]
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in
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@ -158,12 +158,12 @@ def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2),
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"imul{w}\t{$src2, $dst|$dst, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>,
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TB, OpSize;
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TB, OpSize16;
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def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),
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"imul{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>,
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TB, OpSize16;
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TB, OpSize32;
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def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
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(ins GR64:$src1, GR64:$src2),
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"imul{q}\t{$src2, $dst|$dst, $src2}",
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@ -180,14 +180,14 @@ def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst),
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, (load addr:$src2)))],
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IIC_IMUL16_RM>,
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TB, OpSize;
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TB, OpSize16;
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def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst),
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(ins GR32:$src1, i32mem:$src2),
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"imul{l}\t{$src2, $dst|$dst, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, (load addr:$src2)))],
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IIC_IMUL32_RM>,
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TB, OpSize16;
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TB, OpSize32;
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def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst),
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(ins GR64:$src1, i64mem:$src2),
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"imul{q}\t{$src2, $dst|$dst, $src2}",
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@ -209,26 +209,25 @@ def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, imm:$src2))],
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IIC_IMUL16_RRI>, OpSize;
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IIC_IMUL16_RRI>, OpSize16;
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def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8
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(outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag GR16:$src1, i16immSExt8:$src2))],
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IIC_IMUL16_RRI>,
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OpSize;
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IIC_IMUL16_RRI>, OpSize16;
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def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32
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(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, imm:$src2))],
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IIC_IMUL32_RRI>, OpSize16;
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IIC_IMUL32_RRI>, OpSize32;
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def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8
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(outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag GR32:$src1, i32immSExt8:$src2))],
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IIC_IMUL32_RRI>, OpSize16;
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IIC_IMUL32_RRI>, OpSize32;
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def IMUL64rri32 : RIi32S<0x69, MRMSrcReg, // GR64 = GR64*I32
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(outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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@ -251,27 +250,27 @@ def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1), imm:$src2))],
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IIC_IMUL16_RMI>,
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OpSize;
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OpSize16;
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def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8
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(outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2),
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"imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR16:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1),
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i16immSExt8:$src2))], IIC_IMUL16_RMI>,
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OpSize;
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OpSize16;
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def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32
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(outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1), imm:$src2))],
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IIC_IMUL32_RMI>, OpSize16;
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IIC_IMUL32_RMI>, OpSize32;
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def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8
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(outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2),
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"imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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[(set GR32:$dst, EFLAGS,
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(X86smul_flag (load addr:$src1),
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i32immSExt8:$src2))],
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IIC_IMUL32_RMI>, OpSize16;
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IIC_IMUL32_RMI>, OpSize32;
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def IMUL64rmi32 : RIi32S<0x69, MRMSrcMem, // GR64 = [mem64]*I32
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(outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2),
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"imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}",
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@ -300,10 +299,10 @@ def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
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"div{b}\t$src", [], IIC_DIV8_REG>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
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"div{w}\t$src", [], IIC_DIV16>, OpSize;
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"div{w}\t$src", [], IIC_DIV16>, OpSize16;
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
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def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
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"div{l}\t$src", [], IIC_DIV32>, OpSize16;
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"div{l}\t$src", [], IIC_DIV32>, OpSize32;
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// RDX:RAX/r64 = RAX,RDX
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
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def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src),
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@ -317,12 +316,12 @@ def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
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SchedLoadReg<WriteIDivLd>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
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"div{w}\t$src", [], IIC_DIV16>, OpSize,
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"div{w}\t$src", [], IIC_DIV16>, OpSize16,
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SchedLoadReg<WriteIDivLd>;
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
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def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src),
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"div{l}\t$src", [], IIC_DIV32>,
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SchedLoadReg<WriteIDivLd>, OpSize16;
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SchedLoadReg<WriteIDivLd>, OpSize32;
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// RDX:RAX/[mem64] = RAX,RDX
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let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
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def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src),
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@ -337,10 +336,10 @@ def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH
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"idiv{b}\t$src", [], IIC_IDIV8>;
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let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
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def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX
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"idiv{w}\t$src", [], IIC_IDIV16>, OpSize;
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"idiv{w}\t$src", [], IIC_IDIV16>, OpSize16;
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let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in
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def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX
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"idiv{l}\t$src", [], IIC_IDIV32>, OpSize16;
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"idiv{l}\t$src", [], IIC_IDIV32>, OpSize32;
|
||||
// RDX:RAX/r64 = RAX,RDX
|
||||
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in
|
||||
def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src),
|
||||
@ -354,11 +353,11 @@ def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH
|
||||
SchedLoadReg<WriteIDivLd>;
|
||||
let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in
|
||||
def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX
|
||||
"idiv{w}\t$src", [], IIC_IDIV16>, OpSize,
|
||||
"idiv{w}\t$src", [], IIC_IDIV16>, OpSize16,
|
||||
SchedLoadReg<WriteIDivLd>;
|
||||
let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX
|
||||
def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src),
|
||||
"idiv{l}\t$src", [], IIC_IDIV32>, OpSize16,
|
||||
"idiv{l}\t$src", [], IIC_IDIV32>, OpSize32,
|
||||
SchedLoadReg<WriteIDivLd>;
|
||||
let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX
|
||||
def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src),
|
||||
@ -382,11 +381,11 @@ def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"neg{w}\t$dst",
|
||||
[(set GR16:$dst, (ineg GR16:$src1)),
|
||||
(implicit EFLAGS)], IIC_UNARY_REG>, OpSize;
|
||||
(implicit EFLAGS)], IIC_UNARY_REG>, OpSize16;
|
||||
def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"neg{l}\t$dst",
|
||||
[(set GR32:$dst, (ineg GR32:$src1)),
|
||||
(implicit EFLAGS)], IIC_UNARY_REG>, OpSize16;
|
||||
(implicit EFLAGS)], IIC_UNARY_REG>, OpSize32;
|
||||
def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst",
|
||||
[(set GR64:$dst, (ineg GR64:$src1)),
|
||||
(implicit EFLAGS)], IIC_UNARY_REG>;
|
||||
@ -401,11 +400,11 @@ def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst),
|
||||
def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst),
|
||||
"neg{w}\t$dst",
|
||||
[(store (ineg (loadi16 addr:$dst)), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize;
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
|
||||
def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst),
|
||||
"neg{l}\t$dst",
|
||||
[(store (ineg (loadi32 addr:$dst)), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize16;
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>, OpSize32;
|
||||
def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst",
|
||||
[(store (ineg (loadi64 addr:$dst)), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
||||
@ -423,10 +422,10 @@ def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
[(set GR8:$dst, (not GR8:$src1))], IIC_UNARY_REG>;
|
||||
def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"not{w}\t$dst",
|
||||
[(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize;
|
||||
[(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize16;
|
||||
def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"not{l}\t$dst",
|
||||
[(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>, OpSize16;
|
||||
[(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>, OpSize32;
|
||||
def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst",
|
||||
[(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>;
|
||||
}
|
||||
@ -439,11 +438,11 @@ def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst),
|
||||
def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst),
|
||||
"not{w}\t$dst",
|
||||
[(store (not (loadi16 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
|
||||
OpSize;
|
||||
OpSize16;
|
||||
def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst),
|
||||
"not{l}\t$dst",
|
||||
[(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst",
|
||||
[(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>;
|
||||
} // SchedRW
|
||||
@ -462,12 +461,12 @@ let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA.
|
||||
def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"inc{w}\t$dst",
|
||||
[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], IIC_UNARY_REG>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"inc{l}\t$dst",
|
||||
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
|
||||
IIC_UNARY_REG>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst",
|
||||
[(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))],
|
||||
IIC_UNARY_REG>;
|
||||
@ -481,38 +480,38 @@ def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"inc{w}\t$dst",
|
||||
[(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))],
|
||||
IIC_UNARY_REG>,
|
||||
OpSize, Requires<[In64BitMode]>;
|
||||
OpSize16, Requires<[In64BitMode]>;
|
||||
def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"inc{l}\t$dst",
|
||||
[(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))],
|
||||
IIC_UNARY_REG>,
|
||||
OpSize16, Requires<[In64BitMode]>;
|
||||
OpSize32, Requires<[In64BitMode]>;
|
||||
def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"dec{w}\t$dst",
|
||||
[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
|
||||
IIC_UNARY_REG>,
|
||||
OpSize, Requires<[In64BitMode]>;
|
||||
OpSize16, Requires<[In64BitMode]>;
|
||||
def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"dec{l}\t$dst",
|
||||
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
|
||||
IIC_UNARY_REG>,
|
||||
OpSize16, Requires<[In64BitMode]>;
|
||||
OpSize32, Requires<[In64BitMode]>;
|
||||
} // isConvertibleToThreeAddress = 1, CodeSize = 2
|
||||
|
||||
let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
|
||||
CodeSize = 2 in {
|
||||
def INC32_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"inc{w}\t$dst", [], IIC_UNARY_REG>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def INC32_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"inc{l}\t$dst", [], IIC_UNARY_REG>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def DEC32_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"dec{w}\t$dst", [], IIC_UNARY_REG>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def DEC32_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"dec{l}\t$dst", [], IIC_UNARY_REG>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
} // isCodeGenOnly = 1, ForceDisassemble = 1, HasSideEffects = 0, CodeSize = 2
|
||||
|
||||
} // Constraints = "$src1 = $dst", SchedRW
|
||||
@ -524,11 +523,11 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
|
||||
[(store (add (loadi16 addr:$dst), 1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
|
||||
[(store (add (loadi32 addr:$dst), 1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst",
|
||||
[(store (add (loadi64 addr:$dst), 1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
||||
@ -539,19 +538,19 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst",
|
||||
[(store (add (loadi16 addr:$dst), 1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
||||
OpSize, Requires<[In64BitMode]>;
|
||||
OpSize16, Requires<[In64BitMode]>;
|
||||
def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst",
|
||||
[(store (add (loadi32 addr:$dst), 1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
||||
OpSize16, Requires<[In64BitMode]>;
|
||||
OpSize32, Requires<[In64BitMode]>;
|
||||
def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
|
||||
[(store (add (loadi16 addr:$dst), -1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
||||
OpSize, Requires<[In64BitMode]>;
|
||||
OpSize16, Requires<[In64BitMode]>;
|
||||
def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
|
||||
[(store (add (loadi32 addr:$dst), -1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
||||
OpSize16, Requires<[In64BitMode]>;
|
||||
OpSize32, Requires<[In64BitMode]>;
|
||||
} // CodeSize = 2, SchedRW
|
||||
|
||||
let Constraints = "$src1 = $dst", SchedRW = [WriteALU] in {
|
||||
@ -565,12 +564,12 @@ def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"dec{w}\t$dst",
|
||||
[(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))],
|
||||
IIC_UNARY_REG>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"dec{l}\t$dst",
|
||||
[(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))],
|
||||
IIC_UNARY_REG>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst",
|
||||
[(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))],
|
||||
IIC_UNARY_REG>;
|
||||
@ -585,11 +584,11 @@ let CodeSize = 2, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst",
|
||||
[(store (add (loadi16 addr:$dst), -1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst",
|
||||
[(store (add (loadi32 addr:$dst), -1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst",
|
||||
[(store (add (loadi64 addr:$dst), -1), addr:$dst),
|
||||
(implicit EFLAGS)], IIC_UNARY_MEM>;
|
||||
@ -603,7 +602,7 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
|
||||
PatFrag loadnode, X86MemOperand memoperand, ImmType immkind,
|
||||
Operand immoperand, SDPatternOperator immoperator,
|
||||
Operand imm8operand, SDPatternOperator imm8operator,
|
||||
bit hasOddOpcode, bit hasOpSizePrefix, bit hasOpSize16Prefix,
|
||||
bit hasOddOpcode, OperandSize opSize,
|
||||
bit hasREX_WPrefix> {
|
||||
/// VT - This is the value type itself.
|
||||
ValueType VT = vt;
|
||||
@ -654,14 +653,10 @@ class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass,
|
||||
/// other datatypes are odd.
|
||||
bit HasOddOpcode = hasOddOpcode;
|
||||
|
||||
/// HasOpSizePrefix - This bit is set to true if the instruction should have
|
||||
/// the 0x66 operand size prefix in 32-bit or 64-bit modes. This is set for
|
||||
/// i16 types.
|
||||
bit HasOpSizePrefix = hasOpSizePrefix;
|
||||
|
||||
/// HasOpSizePrefix - This bit is set to true if the instruction should have
|
||||
/// the 0x66 operand size prefix in 16-bit mode. This is set for i32 types.
|
||||
bit HasOpSize16Prefix = hasOpSize16Prefix;
|
||||
/// OpSize - Selects whether the instruction needs a 0x66 prefix based on
|
||||
/// 16-bit vs 32-bit mode. i8/i64 set this to OpSizeFixed. i16 sets this
|
||||
/// to Opsize16. i32 sets this to OpSize32.
|
||||
OperandSize OpSize = opSize;
|
||||
|
||||
/// HasREX_WPrefix - This bit is set to true if the instruction should have
|
||||
/// the 0x40 REX prefix. This is set for i64 types.
|
||||
@ -673,16 +668,16 @@ def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">;
|
||||
|
||||
def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem ,
|
||||
Imm8 , i8imm , imm, i8imm , invalid_node,
|
||||
0, 0, 0, 0>;
|
||||
0, OpSizeFixed, 0>;
|
||||
def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem,
|
||||
Imm16, i16imm, imm, i16i8imm, i16immSExt8,
|
||||
1, 1, 0, 0>;
|
||||
1, OpSize16, 0>;
|
||||
def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem,
|
||||
Imm32, i32imm, imm, i32i8imm, i32immSExt8,
|
||||
1, 0, 1, 0>;
|
||||
1, OpSize32, 0>;
|
||||
def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem,
|
||||
Imm32S, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8,
|
||||
1, 0, 0, 1>;
|
||||
1, OpSizeFixed, 1>;
|
||||
|
||||
/// ITy - This instruction base class takes the type info for the instruction.
|
||||
/// Using this, it:
|
||||
@ -702,8 +697,7 @@ class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins,
|
||||
itin> {
|
||||
|
||||
// Infer instruction prefixes from type info.
|
||||
let hasOpSizePrefix = typeinfo.HasOpSizePrefix;
|
||||
let hasOpSize16Prefix = typeinfo.HasOpSize16Prefix;
|
||||
let OpSize = typeinfo.OpSize;
|
||||
let hasREX_WPrefix = typeinfo.HasREX_WPrefix;
|
||||
}
|
||||
|
||||
|
||||
@ -22,13 +22,13 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
|
||||
!strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set GR16:$dst,
|
||||
(X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))],
|
||||
IIC_CMOV16_RR>,TB,OpSize;
|
||||
IIC_CMOV16_RR>, TB, OpSize16;
|
||||
def NAME#32rr
|
||||
: I<opc, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
|
||||
!strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set GR32:$dst,
|
||||
(X86cmov GR32:$src1, GR32:$src2, CondNode, EFLAGS))],
|
||||
IIC_CMOV32_RR>, TB, OpSize16;
|
||||
IIC_CMOV32_RR>, TB, OpSize32;
|
||||
def NAME#64rr
|
||||
:RI<opc, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
|
||||
!strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
|
||||
@ -44,13 +44,13 @@ multiclass CMOV<bits<8> opc, string Mnemonic, PatLeaf CondNode> {
|
||||
!strconcat(Mnemonic, "{w}\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set GR16:$dst, (X86cmov GR16:$src1, (loadi16 addr:$src2),
|
||||
CondNode, EFLAGS))], IIC_CMOV16_RM>,
|
||||
TB, OpSize;
|
||||
TB, OpSize16;
|
||||
def NAME#32rm
|
||||
: I<opc, MRMSrcMem, (outs GR32:$dst), (ins GR32:$src1, i32mem:$src2),
|
||||
!strconcat(Mnemonic, "{l}\t{$src2, $dst|$dst, $src2}"),
|
||||
[(set GR32:$dst, (X86cmov GR32:$src1, (loadi32 addr:$src2),
|
||||
CondNode, EFLAGS))], IIC_CMOV32_RM>,
|
||||
TB, OpSize16;
|
||||
TB, OpSize32;
|
||||
def NAME#64rm
|
||||
:RI<opc, MRMSrcMem, (outs GR64:$dst), (ins GR64:$src1, i64mem:$src2),
|
||||
!strconcat(Mnemonic, "{q}\t{$src2, $dst|$dst, $src2}"),
|
||||
|
||||
@ -320,10 +320,10 @@ def REP_MOVSB_32 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
|
||||
[(X86rep_movs i8)], IIC_REP_MOVS>, REP,
|
||||
Requires<[Not64BitMode]>;
|
||||
def REP_MOVSW_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
|
||||
[(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
|
||||
[(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
|
||||
Requires<[Not64BitMode]>;
|
||||
def REP_MOVSD_32 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
|
||||
[(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize16,
|
||||
[(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
|
||||
Requires<[Not64BitMode]>;
|
||||
}
|
||||
|
||||
@ -332,10 +332,10 @@ def REP_MOVSB_64 : I<0xA4, RawFrm, (outs), (ins), "{rep;movsb|rep movsb}",
|
||||
[(X86rep_movs i8)], IIC_REP_MOVS>, REP,
|
||||
Requires<[In64BitMode]>;
|
||||
def REP_MOVSW_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsw|rep movsw}",
|
||||
[(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize,
|
||||
[(X86rep_movs i16)], IIC_REP_MOVS>, REP, OpSize16,
|
||||
Requires<[In64BitMode]>;
|
||||
def REP_MOVSD_64 : I<0xA5, RawFrm, (outs), (ins), "{rep;movsl|rep movsd}",
|
||||
[(X86rep_movs i32)], IIC_REP_MOVS>, REP,
|
||||
[(X86rep_movs i32)], IIC_REP_MOVS>, REP, OpSize32,
|
||||
Requires<[In64BitMode]>;
|
||||
def REP_MOVSQ_64 : RI<0xA5, RawFrm, (outs), (ins), "{rep;movsq|rep movsq}",
|
||||
[(X86rep_movs i64)], IIC_REP_MOVS>, REP,
|
||||
@ -350,11 +350,11 @@ let Defs = [ECX,EDI], isCodeGenOnly = 1 in {
|
||||
Requires<[Not64BitMode]>;
|
||||
let Uses = [AX,ECX,EDI] in
|
||||
def REP_STOSW_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
|
||||
[(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
|
||||
[(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
|
||||
Requires<[Not64BitMode]>;
|
||||
let Uses = [EAX,ECX,EDI] in
|
||||
def REP_STOSD_32 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
|
||||
[(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize16,
|
||||
[(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
|
||||
Requires<[Not64BitMode]>;
|
||||
}
|
||||
|
||||
@ -365,11 +365,11 @@ let Defs = [RCX,RDI], isCodeGenOnly = 1 in {
|
||||
Requires<[In64BitMode]>;
|
||||
let Uses = [AX,RCX,RDI] in
|
||||
def REP_STOSW_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosw|rep stosw}",
|
||||
[(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize,
|
||||
[(X86rep_stos i16)], IIC_REP_STOS>, REP, OpSize16,
|
||||
Requires<[In64BitMode]>;
|
||||
let Uses = [RAX,RCX,RDI] in
|
||||
def REP_STOSD_64 : I<0xAB, RawFrm, (outs), (ins), "{rep;stosl|rep stosd}",
|
||||
[(X86rep_stos i32)], IIC_REP_STOS>, REP,
|
||||
[(X86rep_stos i32)], IIC_REP_STOS>, REP, OpSize32,
|
||||
Requires<[In64BitMode]>;
|
||||
|
||||
let Uses = [RAX,RCX,RDI] in
|
||||
@ -618,13 +618,13 @@ def NAME#16mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
|
||||
MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
||||
!strconcat(mnemonic, "{w}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[], IIC_ALU_NONMEM>, OpSize, LOCK;
|
||||
[], IIC_ALU_NONMEM>, OpSize16, LOCK;
|
||||
def NAME#32mr : I<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
|
||||
RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
|
||||
MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||
!strconcat(mnemonic, "{l}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[], IIC_ALU_NONMEM>, OpSize16, LOCK;
|
||||
[], IIC_ALU_NONMEM>, OpSize32, LOCK;
|
||||
def NAME#64mr : RI<{RegOpc{7}, RegOpc{6}, RegOpc{5}, RegOpc{4},
|
||||
RegOpc{3}, RegOpc{2}, RegOpc{1}, 1 },
|
||||
MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||
@ -644,14 +644,14 @@ def NAME#16mi : Ii16<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
|
||||
ImmMod, (outs), (ins i16mem :$dst, i16imm :$src2),
|
||||
!strconcat(mnemonic, "{w}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[], IIC_ALU_MEM>, OpSize, LOCK;
|
||||
[], IIC_ALU_MEM>, OpSize16, LOCK;
|
||||
|
||||
def NAME#32mi : Ii32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
|
||||
ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
|
||||
ImmMod, (outs), (ins i32mem :$dst, i32imm :$src2),
|
||||
!strconcat(mnemonic, "{l}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[], IIC_ALU_MEM>, OpSize16, LOCK;
|
||||
[], IIC_ALU_MEM>, OpSize32, LOCK;
|
||||
|
||||
def NAME#64mi32 : RIi32<{ImmOpc{7}, ImmOpc{6}, ImmOpc{5}, ImmOpc{4},
|
||||
ImmOpc{3}, ImmOpc{2}, ImmOpc{1}, 1 },
|
||||
@ -665,13 +665,13 @@ def NAME#16mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
|
||||
ImmMod, (outs), (ins i16mem :$dst, i16i8imm :$src2),
|
||||
!strconcat(mnemonic, "{w}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[], IIC_ALU_MEM>, OpSize, LOCK;
|
||||
[], IIC_ALU_MEM>, OpSize16, LOCK;
|
||||
def NAME#32mi8 : Ii8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
|
||||
ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
|
||||
ImmMod, (outs), (ins i32mem :$dst, i32i8imm :$src2),
|
||||
!strconcat(mnemonic, "{l}\t",
|
||||
"{$src2, $dst|$dst, $src2}"),
|
||||
[], IIC_ALU_MEM>, OpSize16, LOCK;
|
||||
[], IIC_ALU_MEM>, OpSize32, LOCK;
|
||||
def NAME#64mi8 : RIi8<{ImmOpc8{7}, ImmOpc8{6}, ImmOpc8{5}, ImmOpc8{4},
|
||||
ImmOpc8{3}, ImmOpc8{2}, ImmOpc8{1}, 1 },
|
||||
ImmMod, (outs), (ins i64mem :$dst, i64i8imm :$src2),
|
||||
@ -700,10 +700,10 @@ def NAME#8m : I<Opc8, Form, (outs), (ins i8mem :$dst),
|
||||
[], IIC_UNARY_MEM>, LOCK;
|
||||
def NAME#16m : I<Opc, Form, (outs), (ins i16mem:$dst),
|
||||
!strconcat(mnemonic, "{w}\t$dst"),
|
||||
[], IIC_UNARY_MEM>, OpSize, LOCK;
|
||||
[], IIC_UNARY_MEM>, OpSize16, LOCK;
|
||||
def NAME#32m : I<Opc, Form, (outs), (ins i32mem:$dst),
|
||||
!strconcat(mnemonic, "{l}\t$dst"),
|
||||
[], IIC_UNARY_MEM>, OpSize16, LOCK;
|
||||
[], IIC_UNARY_MEM>, OpSize32, LOCK;
|
||||
def NAME#64m : RI<Opc, Form, (outs), (ins i64mem:$dst),
|
||||
!strconcat(mnemonic, "{q}\t$dst"),
|
||||
[], IIC_UNARY_MEM>, LOCK;
|
||||
@ -735,11 +735,11 @@ let isCodeGenOnly = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
let Defs = [AX, EFLAGS], Uses = [AX] in
|
||||
def NAME#16 : I<Opc, Form, (outs), (ins i16mem:$ptr, GR16:$swap),
|
||||
!strconcat(mnemonic, "{w}\t{$swap, $ptr|$ptr, $swap}"),
|
||||
[(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize, LOCK;
|
||||
[(frag addr:$ptr, GR16:$swap, 2)], itin>, TB, OpSize16, LOCK;
|
||||
let Defs = [EAX, EFLAGS], Uses = [EAX] in
|
||||
def NAME#32 : I<Opc, Form, (outs), (ins i32mem:$ptr, GR32:$swap),
|
||||
!strconcat(mnemonic, "{l}\t{$swap, $ptr|$ptr, $swap}"),
|
||||
[(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize16, LOCK;
|
||||
[(frag addr:$ptr, GR32:$swap, 4)], itin>, TB, OpSize32, LOCK;
|
||||
let Defs = [RAX, EFLAGS], Uses = [RAX] in
|
||||
def NAME#64 : RI<Opc, Form, (outs), (ins i64mem:$ptr, GR64:$swap),
|
||||
!strconcat(mnemonic, "{q}\t{$swap, $ptr|$ptr, $swap}"),
|
||||
@ -782,14 +782,14 @@ multiclass ATOMIC_LOAD_BINOP<bits<8> opc8, bits<8> opc, string mnemonic,
|
||||
[(set
|
||||
GR16:$dst,
|
||||
(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
|
||||
itin>, OpSize;
|
||||
itin>, OpSize16;
|
||||
def NAME#32 : I<opc, MRMSrcMem, (outs GR32:$dst),
|
||||
(ins GR32:$val, i32mem:$ptr),
|
||||
!strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR32:$dst,
|
||||
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
|
||||
itin>, OpSize16;
|
||||
itin>, OpSize32;
|
||||
def NAME#64 : RI<opc, MRMSrcMem, (outs GR64:$dst),
|
||||
(ins GR64:$val, i64mem:$ptr),
|
||||
!strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
|
||||
|
||||
@ -23,16 +23,16 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
|
||||
hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
|
||||
def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
|
||||
"ret{l}",
|
||||
[(X86retflag 0)], IIC_RET>, OpSize16, Requires<[Not64BitMode]>;
|
||||
[(X86retflag 0)], IIC_RET>, OpSize32, Requires<[Not64BitMode]>;
|
||||
def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
|
||||
"ret{q}",
|
||||
[(X86retflag 0)], IIC_RET>, Requires<[In64BitMode]>;
|
||||
def RETW : I <0xC3, RawFrm, (outs), (ins),
|
||||
"ret{w}",
|
||||
[], IIC_RET>, OpSize;
|
||||
[], IIC_RET>, OpSize16;
|
||||
def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
|
||||
"ret{l}\t$amt",
|
||||
[(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize16,
|
||||
[(X86retflag timm:$amt)], IIC_RET_IMM>, OpSize32,
|
||||
Requires<[Not64BitMode]>;
|
||||
def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
|
||||
"ret{q}\t$amt",
|
||||
@ -40,27 +40,27 @@ let isTerminator = 1, isReturn = 1, isBarrier = 1,
|
||||
Requires<[In64BitMode]>;
|
||||
def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
|
||||
"ret{w}\t$amt",
|
||||
[], IIC_RET_IMM>, OpSize;
|
||||
[], IIC_RET_IMM>, OpSize16;
|
||||
def LRETL : I <0xCB, RawFrm, (outs), (ins),
|
||||
"{l}ret{l|f}", [], IIC_RET>, OpSize16;
|
||||
"{l}ret{l|f}", [], IIC_RET>, OpSize32;
|
||||
def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
|
||||
"{l}ret{|f}q", [], IIC_RET>, Requires<[In64BitMode]>;
|
||||
def LRETW : I <0xCB, RawFrm, (outs), (ins),
|
||||
"{l}ret{w|f}", [], IIC_RET>, OpSize;
|
||||
"{l}ret{w|f}", [], IIC_RET>, OpSize16;
|
||||
def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
|
||||
"{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize16;
|
||||
"{l}ret{l|f}\t$amt", [], IIC_RET>, OpSize32;
|
||||
def LRETIQ : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
|
||||
"{l}ret{|f}q\t$amt", [], IIC_RET>, Requires<[In64BitMode]>;
|
||||
def LRETIW : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
|
||||
"{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize;
|
||||
"{l}ret{w|f}\t$amt", [], IIC_RET>, OpSize16;
|
||||
}
|
||||
|
||||
// Unconditional branches.
|
||||
let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
|
||||
def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
|
||||
"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize16;
|
||||
"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize32;
|
||||
def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
|
||||
"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize,
|
||||
"jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>, OpSize16,
|
||||
Requires<[In16BitMode]>;
|
||||
let hasSideEffects = 0 in
|
||||
def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
|
||||
@ -74,11 +74,11 @@ let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in {
|
||||
def _1 : Ii8PCRel <opc1, RawFrm, (outs), (ins brtarget8:$dst), asm, [],
|
||||
IIC_Jcc>;
|
||||
def _2 : Ii16PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
|
||||
[(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, OpSize,
|
||||
[(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, OpSize16,
|
||||
TB, Requires<[In16BitMode]>;
|
||||
def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
|
||||
[(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>, TB,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
}
|
||||
}
|
||||
|
||||
@ -126,17 +126,17 @@ let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in
|
||||
let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
||||
def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
|
||||
[(brind GR16:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
|
||||
OpSize, Sched<[WriteJump]>;
|
||||
OpSize16, Sched<[WriteJump]>;
|
||||
def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
|
||||
[(brind (loadi16 addr:$dst))], IIC_JMP_MEM>,
|
||||
Requires<[Not64BitMode]>, OpSize, Sched<[WriteJumpLd]>;
|
||||
Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
|
||||
|
||||
def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
|
||||
[(brind GR32:$dst)], IIC_JMP_REG>, Requires<[Not64BitMode]>,
|
||||
OpSize16, Sched<[WriteJump]>;
|
||||
OpSize32, Sched<[WriteJump]>;
|
||||
def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
|
||||
[(brind (loadi32 addr:$dst))], IIC_JMP_MEM>,
|
||||
Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
|
||||
Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>;
|
||||
|
||||
def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
|
||||
[(brind GR64:$dst)], IIC_JMP_REG>, Requires<[In64BitMode]>,
|
||||
@ -148,20 +148,20 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
|
||||
def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
|
||||
(ins i16imm:$off, i16imm:$seg),
|
||||
"ljmp{w}\t{$seg, $off|$off, $seg}", [],
|
||||
IIC_JMP_FAR_PTR>, OpSize, Sched<[WriteJump]>;
|
||||
IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
|
||||
def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
|
||||
(ins i32imm:$off, i16imm:$seg),
|
||||
"ljmp{l}\t{$seg, $off|$off, $seg}", [],
|
||||
IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
|
||||
IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
|
||||
def FARJMP64 : RI<0xFF, MRM5m, (outs), (ins opaque80mem:$dst),
|
||||
"ljmp{q}\t{*}$dst", [], IIC_JMP_FAR_MEM>,
|
||||
Sched<[WriteJump]>;
|
||||
|
||||
def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaque32mem:$dst),
|
||||
"ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize,
|
||||
"ljmp{w}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
|
||||
Sched<[WriteJumpLd]>;
|
||||
def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaque48mem:$dst),
|
||||
"ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize16,
|
||||
"ljmp{l}\t{*}$dst", [], IIC_JMP_FAR_MEM>, OpSize32,
|
||||
Sched<[WriteJumpLd]>;
|
||||
}
|
||||
|
||||
@ -184,43 +184,43 @@ let isCall = 1 in
|
||||
let Uses = [ESP] in {
|
||||
def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
|
||||
(outs), (ins i32imm_pcrel:$dst),
|
||||
"call{l}\t$dst", [], IIC_CALL_RI>, OpSize16,
|
||||
"call{l}\t$dst", [], IIC_CALL_RI>, OpSize32,
|
||||
Requires<[Not64BitMode]>, Sched<[WriteJump]>;
|
||||
def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
|
||||
(outs), (ins i16imm_pcrel:$dst),
|
||||
"call{w}\t$dst", [], IIC_CALL_RI>, OpSize,
|
||||
"call{w}\t$dst", [], IIC_CALL_RI>, OpSize16,
|
||||
Sched<[WriteJump]>;
|
||||
def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
|
||||
"call{w}\t{*}$dst", [(X86call GR16:$dst)], IIC_CALL_RI>,
|
||||
OpSize, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
|
||||
OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
|
||||
def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
|
||||
"call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))],
|
||||
IIC_CALL_MEM>, OpSize,
|
||||
IIC_CALL_MEM>, OpSize16,
|
||||
Requires<[Not64BitMode,FavorMemIndirectCall]>,
|
||||
Sched<[WriteJumpLd]>;
|
||||
def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
|
||||
"call{l}\t{*}$dst", [(X86call GR32:$dst)], IIC_CALL_RI>,
|
||||
OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
|
||||
OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
|
||||
def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
|
||||
"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))],
|
||||
IIC_CALL_MEM>, OpSize16,
|
||||
IIC_CALL_MEM>, OpSize32,
|
||||
Requires<[Not64BitMode,FavorMemIndirectCall]>,
|
||||
Sched<[WriteJumpLd]>;
|
||||
|
||||
def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
|
||||
(ins i16imm:$off, i16imm:$seg),
|
||||
"lcall{w}\t{$seg, $off|$off, $seg}", [],
|
||||
IIC_CALL_FAR_PTR>, OpSize, Sched<[WriteJump]>;
|
||||
IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
|
||||
def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
|
||||
(ins i32imm:$off, i16imm:$seg),
|
||||
"lcall{l}\t{$seg, $off|$off, $seg}", [],
|
||||
IIC_CALL_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
|
||||
IIC_CALL_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
|
||||
|
||||
def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaque32mem:$dst),
|
||||
"lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize,
|
||||
"lcall{w}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
|
||||
Sched<[WriteJumpLd]>;
|
||||
def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaque48mem:$dst),
|
||||
"lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize16,
|
||||
"lcall{l}\t{*}$dst", [], IIC_CALL_FAR_MEM>, OpSize32,
|
||||
Sched<[WriteJumpLd]>;
|
||||
}
|
||||
|
||||
|
||||
@ -14,17 +14,17 @@
|
||||
let neverHasSideEffects = 1 in {
|
||||
let Defs = [AX], Uses = [AL] in
|
||||
def CBW : I<0x98, RawFrm, (outs), (ins),
|
||||
"{cbtw|cbw}", [], IIC_CBW>, OpSize; // AX = signext(AL)
|
||||
"{cbtw|cbw}", [], IIC_CBW>, OpSize16; // AX = signext(AL)
|
||||
let Defs = [EAX], Uses = [AX] in
|
||||
def CWDE : I<0x98, RawFrm, (outs), (ins),
|
||||
"{cwtl|cwde}", [], IIC_CBW>, OpSize16; // EAX = signext(AX)
|
||||
"{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
|
||||
|
||||
let Defs = [AX,DX], Uses = [AX] in
|
||||
def CWD : I<0x99, RawFrm, (outs), (ins),
|
||||
"{cwtd|cwd}", [], IIC_CBW>, OpSize; // DX:AX = signext(AX)
|
||||
"{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
|
||||
let Defs = [EAX,EDX], Uses = [EAX] in
|
||||
def CDQ : I<0x99, RawFrm, (outs), (ins),
|
||||
"{cltd|cdq}", [], IIC_CBW>, OpSize16; // EDX:EAX = signext(EAX)
|
||||
"{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX)
|
||||
|
||||
|
||||
let Defs = [RAX], Uses = [EAX] in
|
||||
@ -42,54 +42,54 @@ let neverHasSideEffects = 1 in {
|
||||
let neverHasSideEffects = 1 in {
|
||||
def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
|
||||
"movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
|
||||
TB, OpSize, Sched<[WriteALU]>;
|
||||
TB, OpSize16, Sched<[WriteALU]>;
|
||||
let mayLoad = 1 in
|
||||
def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
|
||||
"movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_M8>,
|
||||
TB, OpSize, Sched<[WriteALULd]>;
|
||||
TB, OpSize16, Sched<[WriteALULd]>;
|
||||
} // neverHasSideEffects = 1
|
||||
def MOVSX32rr8 : I<0xBE, MRMSrcReg, (outs GR32:$dst), (ins GR8:$src),
|
||||
"movs{bl|x}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (sext GR8:$src))], IIC_MOVSX>, TB,
|
||||
OpSize16, Sched<[WriteALU]>;
|
||||
OpSize32, Sched<[WriteALU]>;
|
||||
def MOVSX32rm8 : I<0xBE, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
|
||||
"movs{bl|x}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (sextloadi32i8 addr:$src))], IIC_MOVSX>, TB,
|
||||
OpSize16, Sched<[WriteALULd]>;
|
||||
OpSize32, Sched<[WriteALULd]>;
|
||||
def MOVSX32rr16: I<0xBF, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
|
||||
"movs{wl|x}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (sext GR16:$src))], IIC_MOVSX>, TB,
|
||||
OpSize16, Sched<[WriteALU]>;
|
||||
OpSize32, Sched<[WriteALU]>;
|
||||
def MOVSX32rm16: I<0xBF, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
|
||||
"movs{wl|x}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (sextloadi32i16 addr:$src))], IIC_MOVSX>,
|
||||
OpSize16, TB, Sched<[WriteALULd]>;
|
||||
OpSize32, TB, Sched<[WriteALULd]>;
|
||||
|
||||
let neverHasSideEffects = 1 in {
|
||||
def MOVZX16rr8 : I<0xB6, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
|
||||
"movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_R8>,
|
||||
TB, OpSize, Sched<[WriteALU]>;
|
||||
TB, OpSize16, Sched<[WriteALU]>;
|
||||
let mayLoad = 1 in
|
||||
def MOVZX16rm8 : I<0xB6, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
|
||||
"movz{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX_R16_M8>,
|
||||
TB, OpSize, Sched<[WriteALULd]>;
|
||||
TB, OpSize16, Sched<[WriteALULd]>;
|
||||
} // neverHasSideEffects = 1
|
||||
def MOVZX32rr8 : I<0xB6, MRMSrcReg, (outs GR32:$dst), (ins GR8 :$src),
|
||||
"movz{bl|x}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (zext GR8:$src))], IIC_MOVZX>, TB,
|
||||
OpSize16, Sched<[WriteALU]>;
|
||||
OpSize32, Sched<[WriteALU]>;
|
||||
def MOVZX32rm8 : I<0xB6, MRMSrcMem, (outs GR32:$dst), (ins i8mem :$src),
|
||||
"movz{bl|x}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (zextloadi32i8 addr:$src))], IIC_MOVZX>, TB,
|
||||
OpSize16, Sched<[WriteALULd]>;
|
||||
OpSize32, Sched<[WriteALULd]>;
|
||||
def MOVZX32rr16: I<0xB7, MRMSrcReg, (outs GR32:$dst), (ins GR16:$src),
|
||||
"movz{wl|x}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (zext GR16:$src))], IIC_MOVZX>, TB,
|
||||
OpSize16, Sched<[WriteALU]>;
|
||||
OpSize32, Sched<[WriteALU]>;
|
||||
def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
|
||||
"movz{wl|x}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (zextloadi32i16 addr:$src))], IIC_MOVZX>,
|
||||
TB, OpSize16, Sched<[WriteALULd]>;
|
||||
TB, OpSize32, Sched<[WriteALULd]>;
|
||||
|
||||
// These are the same as the regular MOVZX32rr8 and MOVZX32rm8
|
||||
// except that they use GR32_NOREX for the output operand register class
|
||||
|
||||
@ -152,10 +152,18 @@ def EncVEX : Encoding<1>;
|
||||
def EncXOP : Encoding<2>;
|
||||
def EncEVEX : Encoding<3>;
|
||||
|
||||
// Operand size for encodings that change based on mode.
|
||||
class OperandSize<bits<2> val> {
|
||||
bits<2> Value = val;
|
||||
}
|
||||
def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
|
||||
def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
|
||||
def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
|
||||
|
||||
// Prefix byte classes which are used to indicate to the ad-hoc machine code
|
||||
// emitter that various prefix bytes are required.
|
||||
class OpSize { bit hasOpSizePrefix = 1; }
|
||||
class OpSize16 { bit hasOpSize16Prefix = 1; }
|
||||
class OpSize16 { OperandSize OpSize = OpSize16; }
|
||||
class OpSize32 { OperandSize OpSize = OpSize32; }
|
||||
class AdSize { bit hasAdSizePrefix = 1; }
|
||||
class REX_W { bit hasREX_WPrefix = 1; }
|
||||
class LOCK { bit hasLockPrefix = 1; }
|
||||
@ -239,8 +247,8 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
|
||||
// isCodeGenonly. Needed to hide an ambiguous
|
||||
// AsmString from the parser, but still disassemble.
|
||||
|
||||
bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix?
|
||||
bit hasOpSize16Prefix = 0;// Does this inst have a 0x66 prefix in 16-bit mode?
|
||||
OperandSize OpSize = OpSizeFixed; // Does this instruction's encoding change
|
||||
// based on operand size of the mode
|
||||
bit hasAdSizePrefix = 0; // Does this inst have a 0x67 prefix?
|
||||
|
||||
Prefix OpPrefix = NoPrfx; // Which prefix byte does this inst have?
|
||||
@ -271,8 +279,7 @@ class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
|
||||
|
||||
// TSFlags layout should be kept in sync with X86InstrInfo.h.
|
||||
let TSFlags{5-0} = FormBits;
|
||||
let TSFlags{6} = hasOpSizePrefix;
|
||||
let TSFlags{7} = hasOpSize16Prefix;
|
||||
let TSFlags{7-6} = OpSize.Value;
|
||||
let TSFlags{8} = hasAdSizePrefix;
|
||||
let TSFlags{10-9} = OpPrefix.Value;
|
||||
let TSFlags{15-11} = OpMap.Value;
|
||||
|
||||
@ -932,9 +932,9 @@ def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
|
||||
let neverHasSideEffects = 1, SchedRW = [WriteZero] in {
|
||||
def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
|
||||
def NOOPW : I<0x1f, MRM0m, (outs), (ins i16mem:$zero),
|
||||
"nop{w}\t$zero", [], IIC_NOP>, TB, OpSize;
|
||||
"nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
|
||||
def NOOPL : I<0x1f, MRM0m, (outs), (ins i32mem:$zero),
|
||||
"nop{l}\t$zero", [], IIC_NOP>, TB;
|
||||
"nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
|
||||
}
|
||||
|
||||
|
||||
@ -961,54 +961,55 @@ def LEAVE64 : I<0xC9, RawFrm,
|
||||
let Defs = [ESP], Uses = [ESP], neverHasSideEffects=1 in {
|
||||
let mayLoad = 1, SchedRW = [WriteLoad] in {
|
||||
def POP16r : I<0x58, AddRegFrm, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
|
||||
IIC_POP_REG16>, OpSize;
|
||||
IIC_POP_REG16>, OpSize16;
|
||||
def POP32r : I<0x58, AddRegFrm, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
|
||||
IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
|
||||
IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
|
||||
def POP16rmr: I<0x8F, MRM0r, (outs GR16:$reg), (ins), "pop{w}\t$reg", [],
|
||||
IIC_POP_REG>, OpSize;
|
||||
IIC_POP_REG>, OpSize16;
|
||||
def POP16rmm: I<0x8F, MRM0m, (outs), (ins i16mem:$dst), "pop{w}\t$dst", [],
|
||||
IIC_POP_MEM>, OpSize;
|
||||
IIC_POP_MEM>, OpSize16;
|
||||
def POP32rmr: I<0x8F, MRM0r, (outs GR32:$reg), (ins), "pop{l}\t$reg", [],
|
||||
IIC_POP_REG>, OpSize16, Requires<[Not64BitMode]>;
|
||||
IIC_POP_REG>, OpSize32, Requires<[Not64BitMode]>;
|
||||
def POP32rmm: I<0x8F, MRM0m, (outs), (ins i32mem:$dst), "pop{l}\t$dst", [],
|
||||
IIC_POP_MEM>, Requires<[Not64BitMode]>;
|
||||
|
||||
def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>, OpSize;
|
||||
def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", [], IIC_POP_F>,
|
||||
OpSize16;
|
||||
def POPF32 : I<0x9D, RawFrm, (outs), (ins), "popf{l|d}", [], IIC_POP_FD>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
} // mayLoad, SchedRW
|
||||
|
||||
let mayStore = 1, SchedRW = [WriteStore] in {
|
||||
def PUSH16r : I<0x50, AddRegFrm, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
|
||||
IIC_PUSH_REG>, OpSize;
|
||||
IIC_PUSH_REG>, OpSize16;
|
||||
def PUSH32r : I<0x50, AddRegFrm, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
|
||||
IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
|
||||
IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
|
||||
def PUSH16rmr: I<0xFF, MRM6r, (outs), (ins GR16:$reg), "push{w}\t$reg",[],
|
||||
IIC_PUSH_REG>, OpSize;
|
||||
IIC_PUSH_REG>, OpSize16;
|
||||
def PUSH16rmm: I<0xFF, MRM6m, (outs), (ins i16mem:$src), "push{w}\t$src",[],
|
||||
IIC_PUSH_MEM>, OpSize;
|
||||
IIC_PUSH_MEM>, OpSize16;
|
||||
def PUSH32rmr: I<0xFF, MRM6r, (outs), (ins GR32:$reg), "push{l}\t$reg",[],
|
||||
IIC_PUSH_REG>, OpSize16, Requires<[Not64BitMode]>;
|
||||
IIC_PUSH_REG>, OpSize32, Requires<[Not64BitMode]>;
|
||||
def PUSH32rmm: I<0xFF, MRM6m, (outs), (ins i32mem:$src), "push{l}\t$src",[],
|
||||
IIC_PUSH_MEM>, OpSize16, Requires<[Not64BitMode]>;
|
||||
IIC_PUSH_MEM>, OpSize32, Requires<[Not64BitMode]>;
|
||||
|
||||
def PUSH16i8 : Ii8<0x6a, RawFrm, (outs), (ins i16i8imm:$imm),
|
||||
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
|
||||
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
|
||||
Requires<[Not64BitMode]>;
|
||||
def PUSH32i8 : Ii8<0x6a, RawFrm, (outs), (ins i32i8imm:$imm),
|
||||
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
|
||||
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
|
||||
Requires<[Not64BitMode]>;
|
||||
def PUSHi16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
|
||||
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
|
||||
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
|
||||
Requires<[Not64BitMode]>;
|
||||
def PUSHi32 : Ii32<0x68, RawFrm, (outs), (ins i32imm:$imm),
|
||||
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
|
||||
"push{l}\t$imm", [], IIC_PUSH_IMM>, OpSize32,
|
||||
Requires<[Not64BitMode]>;
|
||||
|
||||
def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", [], IIC_PUSH_F>,
|
||||
OpSize;
|
||||
OpSize16;
|
||||
def PUSHF32 : I<0x9C, RawFrm, (outs), (ins), "pushf{l|d}", [], IIC_PUSH_F>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
|
||||
} // mayStore, SchedRW
|
||||
}
|
||||
@ -1037,7 +1038,7 @@ let Defs = [RSP], Uses = [RSP], neverHasSideEffects = 1, mayStore = 1,
|
||||
def PUSH64i8 : Ii8<0x6a, RawFrm, (outs), (ins i64i8imm:$imm),
|
||||
"push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
|
||||
def PUSH64i16 : Ii16<0x68, RawFrm, (outs), (ins i16imm:$imm),
|
||||
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize,
|
||||
"push{w}\t$imm", [], IIC_PUSH_IMM>, OpSize16,
|
||||
Requires<[In64BitMode]>;
|
||||
def PUSH64i32 : Ii32S<0x68, RawFrm, (outs), (ins i64i32imm:$imm),
|
||||
"push{q}\t$imm", [], IIC_PUSH_IMM>, Requires<[In64BitMode]>;
|
||||
@ -1053,16 +1054,16 @@ def PUSHF64 : I<0x9C, RawFrm, (outs), (ins), "pushfq", [], IIC_PUSH_F>,
|
||||
let Defs = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP], Uses = [ESP],
|
||||
mayLoad = 1, neverHasSideEffects = 1, SchedRW = [WriteLoad] in {
|
||||
def POPA32 : I<0x61, RawFrm, (outs), (ins), "popal", [], IIC_POP_A>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def POPA16 : I<0x61, RawFrm, (outs), (ins), "popaw", [], IIC_POP_A>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
}
|
||||
let Defs = [ESP], Uses = [EDI, ESI, EBP, EBX, EDX, ECX, EAX, ESP],
|
||||
mayStore = 1, neverHasSideEffects = 1, SchedRW = [WriteStore] in {
|
||||
def PUSHA32 : I<0x60, RawFrm, (outs), (ins), "pushal", [], IIC_PUSH_A>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def PUSHA16 : I<0x60, RawFrm, (outs), (ins), "pushaw", [], IIC_PUSH_A>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
}
|
||||
|
||||
let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
|
||||
@ -1070,7 +1071,7 @@ let Constraints = "$src = $dst", SchedRW = [WriteALU] in {
|
||||
def BSWAP32r : I<0xC8, AddRegFrm,
|
||||
(outs GR32:$dst), (ins GR32:$src),
|
||||
"bswap{l}\t$dst",
|
||||
[(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize16, TB;
|
||||
[(set GR32:$dst, (bswap GR32:$src))], IIC_BSWAP>, OpSize32, TB;
|
||||
|
||||
def BSWAP64r : RI<0xC8, AddRegFrm, (outs GR64:$dst), (ins GR64:$src),
|
||||
"bswap{q}\t$dst",
|
||||
@ -1082,20 +1083,20 @@ let Defs = [EFLAGS] in {
|
||||
def BSF16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"bsf{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, EFLAGS, (X86bsf GR16:$src))],
|
||||
IIC_BIT_SCAN_REG>, TB, OpSize, Sched<[WriteShift]>;
|
||||
IIC_BIT_SCAN_REG>, TB, OpSize16, Sched<[WriteShift]>;
|
||||
def BSF16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"bsf{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, EFLAGS, (X86bsf (loadi16 addr:$src)))],
|
||||
IIC_BIT_SCAN_MEM>, TB, OpSize, Sched<[WriteShiftLd]>;
|
||||
IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
|
||||
def BSF32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"bsf{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, EFLAGS, (X86bsf GR32:$src))],
|
||||
IIC_BIT_SCAN_REG>, TB, OpSize16,
|
||||
IIC_BIT_SCAN_REG>, TB, OpSize32,
|
||||
Sched<[WriteShift]>;
|
||||
def BSF32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||
"bsf{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, EFLAGS, (X86bsf (loadi32 addr:$src)))],
|
||||
IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
|
||||
IIC_BIT_SCAN_MEM>, TB, OpSize32, Sched<[WriteShiftLd]>;
|
||||
def BSF64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
||||
"bsf{q}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR64:$dst, EFLAGS, (X86bsf GR64:$src))],
|
||||
@ -1109,21 +1110,21 @@ def BSR16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"bsr{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, EFLAGS, (X86bsr GR16:$src))],
|
||||
IIC_BIT_SCAN_REG>,
|
||||
TB, OpSize, Sched<[WriteShift]>;
|
||||
TB, OpSize16, Sched<[WriteShift]>;
|
||||
def BSR16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"bsr{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, EFLAGS, (X86bsr (loadi16 addr:$src)))],
|
||||
IIC_BIT_SCAN_MEM>, TB,
|
||||
OpSize, Sched<[WriteShiftLd]>;
|
||||
OpSize16, Sched<[WriteShiftLd]>;
|
||||
def BSR32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"bsr{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, EFLAGS, (X86bsr GR32:$src))],
|
||||
IIC_BIT_SCAN_REG>, TB, OpSize16,
|
||||
IIC_BIT_SCAN_REG>, TB, OpSize32,
|
||||
Sched<[WriteShift]>;
|
||||
def BSR32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||
"bsr{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, EFLAGS, (X86bsr (loadi32 addr:$src)))],
|
||||
IIC_BIT_SCAN_MEM>, TB, OpSize16, Sched<[WriteShiftLd]>;
|
||||
IIC_BIT_SCAN_MEM>, TB, OpSize32, Sched<[WriteShiftLd]>;
|
||||
def BSR64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
||||
"bsr{q}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR64:$dst, EFLAGS, (X86bsr GR64:$src))], IIC_BIT_SCAN_REG>, TB,
|
||||
@ -1140,9 +1141,9 @@ let Defs = [EDI,ESI], Uses = [EDI,ESI,EFLAGS] in {
|
||||
def MOVSB : I<0xA4, RawFrmDstSrc, (outs dstidx8:$dst), (ins srcidx8:$src),
|
||||
"movsb\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
|
||||
def MOVSW : I<0xA5, RawFrmDstSrc, (outs dstidx16:$dst), (ins srcidx16:$src),
|
||||
"movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize;
|
||||
"movsw\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
|
||||
def MOVSL : I<0xA5, RawFrmDstSrc, (outs dstidx32:$dst), (ins srcidx32:$src),
|
||||
"movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize16;
|
||||
"movs{l|d}\t{$src, $dst|$dst, $src}", [], IIC_MOVS>, OpSize32;
|
||||
def MOVSQ : RI<0xA5, RawFrmDstSrc, (outs dstidx64:$dst), (ins srcidx64:$src),
|
||||
"movsq\t{$src, $dst|$dst, $src}", [], IIC_MOVS>;
|
||||
}
|
||||
@ -1153,10 +1154,10 @@ def STOSB : I<0xAA, RawFrmDst, (outs dstidx8:$dst), (ins),
|
||||
"stosb\t{%al, $dst|$dst, al}", [], IIC_STOS>;
|
||||
let Defs = [EDI], Uses = [AX,EDI,EFLAGS] in
|
||||
def STOSW : I<0xAB, RawFrmDst, (outs dstidx16:$dst), (ins),
|
||||
"stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize;
|
||||
"stosw\t{%ax, $dst|$dst, ax}", [], IIC_STOS>, OpSize16;
|
||||
let Defs = [EDI], Uses = [EAX,EDI,EFLAGS] in
|
||||
def STOSL : I<0xAB, RawFrmDst, (outs dstidx32:$dst), (ins),
|
||||
"stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize16;
|
||||
"stos{l|d}\t{%eax, $dst|$dst, eax}", [], IIC_STOS>, OpSize32;
|
||||
let Defs = [RCX,RDI], Uses = [RAX,RCX,RDI,EFLAGS] in
|
||||
def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
|
||||
"stosq\t{%rax, $dst|$dst, rax}", [], IIC_STOS>;
|
||||
@ -1164,18 +1165,18 @@ def STOSQ : RI<0xAB, RawFrmDst, (outs dstidx64:$dst), (ins),
|
||||
def SCAS8 : I<0xAE, RawFrmDst, (outs), (ins dstidx8:$dst),
|
||||
"scasb\t{$dst, %al|al, $dst}", [], IIC_SCAS>;
|
||||
def SCAS16 : I<0xAF, RawFrmDst, (outs), (ins dstidx16:$dst),
|
||||
"scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize;
|
||||
"scasw\t{$dst, %ax|ax, $dst}", [], IIC_SCAS>, OpSize16;
|
||||
def SCAS32 : I<0xAF, RawFrmDst, (outs), (ins dstidx32:$dst),
|
||||
"scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize16;
|
||||
"scas{l|d}\t{$dst, %eax|eax, $dst}", [], IIC_SCAS>, OpSize32;
|
||||
def SCAS64 : RI<0xAF, RawFrmDst, (outs), (ins dstidx64:$dst),
|
||||
"scasq\t{$dst, %rax|rax, $dst}", [], IIC_SCAS>;
|
||||
|
||||
def CMPS8 : I<0xA6, RawFrmDstSrc, (outs), (ins dstidx8:$dst, srcidx8:$src),
|
||||
"cmpsb\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
|
||||
def CMPS16 : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx16:$dst, srcidx16:$src),
|
||||
"cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize;
|
||||
"cmpsw\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
|
||||
def CMPS32 : I<0xA7, RawFrmDstSrc, (outs), (ins dstidx32:$dst, srcidx32:$src),
|
||||
"cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize16;
|
||||
"cmps{l|d}\t{$dst, $src|$src, $dst}", [], IIC_CMPS>, OpSize32;
|
||||
def CMPS64 : RI<0xA7, RawFrmDstSrc, (outs), (ins dstidx64:$dst, srcidx64:$src),
|
||||
"cmpsq\t{$dst, $src|$src, $dst}", [], IIC_CMPS>;
|
||||
} // SchedRW
|
||||
@ -1188,9 +1189,9 @@ let neverHasSideEffects = 1 in {
|
||||
def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
|
||||
"mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
|
||||
def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
|
||||
def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
|
||||
def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
||||
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
|
||||
}
|
||||
@ -1201,10 +1202,10 @@ def MOV8ri : Ii8 <0xB0, AddRegFrm, (outs GR8 :$dst), (ins i8imm :$src),
|
||||
[(set GR8:$dst, imm:$src)], IIC_MOV>;
|
||||
def MOV16ri : Ii16<0xB8, AddRegFrm, (outs GR16:$dst), (ins i16imm:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize;
|
||||
[(set GR16:$dst, imm:$src)], IIC_MOV>, OpSize16;
|
||||
def MOV32ri : Ii32<0xB8, AddRegFrm, (outs GR32:$dst), (ins i32imm:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize16;
|
||||
[(set GR32:$dst, imm:$src)], IIC_MOV>, OpSize32;
|
||||
def MOV64ri : RIi64<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64imm:$src),
|
||||
"movabs{q}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR64:$dst, imm:$src)], IIC_MOV>;
|
||||
@ -1220,10 +1221,10 @@ def MOV8mi : Ii8 <0xC6, MRM0m, (outs), (ins i8mem :$dst, i8imm :$src),
|
||||
[(store (i8 imm:$src), addr:$dst)], IIC_MOV_MEM>;
|
||||
def MOV16mi : Ii16<0xC7, MRM0m, (outs), (ins i16mem:$dst, i16imm:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}",
|
||||
[(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize;
|
||||
[(store (i16 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
|
||||
def MOV32mi : Ii32<0xC7, MRM0m, (outs), (ins i32mem:$dst, i32imm:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}",
|
||||
[(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize16;
|
||||
[(store (i32 imm:$src), addr:$dst)], IIC_MOV_MEM>, OpSize32;
|
||||
def MOV64mi32 : RIi32S<0xC7, MRM0m, (outs), (ins i64mem:$dst, i64i32imm:$src),
|
||||
"mov{q}\t{$src, $dst|$dst, $src}",
|
||||
[(store i64immSExt32:$src, addr:$dst)], IIC_MOV_MEM>;
|
||||
@ -1239,42 +1240,42 @@ def MOV8o8a : Ii32 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
|
||||
"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
|
||||
Requires<[In32BitMode]>;
|
||||
def MOV16o16a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
|
||||
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
|
||||
Requires<[In32BitMode]>;
|
||||
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
|
||||
OpSize16, Requires<[In32BitMode]>;
|
||||
def MOV32o32a : Ii32 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
|
||||
"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
|
||||
OpSize16, Requires<[In32BitMode]>;
|
||||
OpSize32, Requires<[In32BitMode]>;
|
||||
|
||||
def MOV8o8a_16 : Ii16 <0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
|
||||
"mov{b}\t{$src, %al|al, $src}", [], IIC_MOV_MEM>,
|
||||
AdSize, Requires<[In16BitMode]>;
|
||||
def MOV16o16a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
|
||||
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>, OpSize,
|
||||
AdSize, Requires<[In16BitMode]>;
|
||||
"mov{w}\t{$src, %ax|ax, $src}", [], IIC_MOV_MEM>,
|
||||
OpSize16, AdSize, Requires<[In16BitMode]>;
|
||||
def MOV32o32a_16 : Ii16 <0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
|
||||
"mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>,
|
||||
AdSize, OpSize16, Requires<[In16BitMode]>;
|
||||
AdSize, OpSize32, Requires<[In16BitMode]>;
|
||||
}
|
||||
let mayStore = 1 in {
|
||||
def MOV8ao8 : Ii32 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
|
||||
"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
|
||||
Requires<[In32BitMode]>;
|
||||
def MOV16ao16 : Ii32 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
|
||||
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
|
||||
Requires<[In32BitMode]>;
|
||||
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
|
||||
OpSize16, Requires<[In32BitMode]>;
|
||||
def MOV32ao32 : Ii32 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
|
||||
"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
|
||||
OpSize16, Requires<[In32BitMode]>;
|
||||
OpSize32, Requires<[In32BitMode]>;
|
||||
|
||||
def MOV8ao8_16 : Ii16 <0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
|
||||
"mov{b}\t{%al, $dst|$dst, al}", [], IIC_MOV_MEM>,
|
||||
AdSize, Requires<[In16BitMode]>;
|
||||
def MOV16ao16_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
|
||||
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>, OpSize,
|
||||
AdSize, Requires<[In16BitMode]>;
|
||||
"mov{w}\t{%ax, $dst|$dst, ax}", [], IIC_MOV_MEM>,
|
||||
OpSize16, AdSize, Requires<[In16BitMode]>;
|
||||
def MOV32ao32_16 : Ii16 <0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
|
||||
"mov{l}\t{%eax, $dst|$dst, eax}", [], IIC_MOV_MEM>,
|
||||
OpSize16, AdSize, Requires<[In16BitMode]>;
|
||||
OpSize32, AdSize, Requires<[In16BitMode]>;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1285,10 +1286,10 @@ def MOV64o8a : RIi64_NOREX<0xA0, RawFrmMemOffs, (outs), (ins offset8:$src),
|
||||
"movabs{b}\t{$src, %al|al, $src}", []>,
|
||||
Requires<[In64BitMode]>;
|
||||
def MOV64o16a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset16:$src),
|
||||
"movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize,
|
||||
"movabs{w}\t{$src, %ax|ax, $src}", []>, OpSize16,
|
||||
Requires<[In64BitMode]>;
|
||||
def MOV64o32a : RIi64_NOREX<0xA1, RawFrmMemOffs, (outs), (ins offset32:$src),
|
||||
"movabs{l}\t{$src, %eax|eax, $src}", []>,
|
||||
"movabs{l}\t{$src, %eax|eax, $src}", []>, OpSize32,
|
||||
Requires<[In64BitMode]>;
|
||||
def MOV64o64a : RIi64<0xA1, RawFrmMemOffs, (outs), (ins offset64:$src),
|
||||
"movabs{q}\t{$src, %rax|rax, $src}", []>,
|
||||
@ -1300,10 +1301,10 @@ def MOV64ao8 : RIi64_NOREX<0xA2, RawFrmMemOffs, (outs offset8:$dst), (ins),
|
||||
"movabs{b}\t{%al, $dst|$dst, al}", []>,
|
||||
Requires<[In64BitMode]>;
|
||||
def MOV64ao16 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset16:$dst), (ins),
|
||||
"movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize,
|
||||
"movabs{w}\t{%ax, $dst|$dst, ax}", []>, OpSize16,
|
||||
Requires<[In64BitMode]>;
|
||||
def MOV64ao32 : RIi64_NOREX<0xA3, RawFrmMemOffs, (outs offset32:$dst), (ins),
|
||||
"movabs{l}\t{%eax, $dst|$dst, eax}", []>,
|
||||
"movabs{l}\t{%eax, $dst|$dst, eax}", []>, OpSize32,
|
||||
Requires<[In64BitMode]>;
|
||||
def MOV64ao64 : RIi64<0xA3, RawFrmMemOffs, (outs offset64:$dst), (ins),
|
||||
"movabs{q}\t{%rax, $dst|$dst, rax}", []>,
|
||||
@ -1316,9 +1317,9 @@ let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0,
|
||||
def MOV8rr_REV : I<0x8A, MRMSrcReg, (outs GR8:$dst), (ins GR8:$src),
|
||||
"mov{b}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
|
||||
def MOV16rr_REV : I<0x8B, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize;
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
|
||||
def MOV32rr_REV : I<0x8B, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize16;
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV>, OpSize32;
|
||||
def MOV64rr_REV : RI<0x8B, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
||||
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV>;
|
||||
}
|
||||
@ -1329,10 +1330,10 @@ def MOV8rm : I<0x8A, MRMSrcMem, (outs GR8 :$dst), (ins i8mem :$src),
|
||||
[(set GR8:$dst, (loadi8 addr:$src))], IIC_MOV_MEM>;
|
||||
def MOV16rm : I<0x8B, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize;
|
||||
[(set GR16:$dst, (loadi16 addr:$src))], IIC_MOV_MEM>, OpSize16;
|
||||
def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize16;
|
||||
[(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32;
|
||||
def MOV64rm : RI<0x8B, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
||||
"mov{q}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR64:$dst, (load addr:$src))], IIC_MOV_MEM>;
|
||||
@ -1344,10 +1345,10 @@ def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src),
|
||||
[(store GR8:$src, addr:$dst)], IIC_MOV_MEM>;
|
||||
def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}",
|
||||
[(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize;
|
||||
[(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
|
||||
def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}",
|
||||
[(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16;
|
||||
[(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32;
|
||||
def MOV64mr : RI<0x89, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
||||
"mov{q}\t{$src, $dst|$dst, $src}",
|
||||
[(store GR64:$src, addr:$dst)], IIC_MOV_MEM>;
|
||||
@ -1394,11 +1395,11 @@ let SchedRW = [WriteALU] in {
|
||||
def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
||||
"bt{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86bt GR16:$src1, GR16:$src2))], IIC_BT_RR>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
||||
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86bt GR32:$src1, GR32:$src2))], IIC_BT_RR>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86bt GR64:$src1, GR64:$src2))], IIC_BT_RR>, TB;
|
||||
@ -1415,13 +1416,13 @@ let mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteALULd] in {
|
||||
// [(X86bt (loadi16 addr:$src1), GR16:$src2),
|
||||
// (implicit EFLAGS)]
|
||||
[], IIC_BT_MR
|
||||
>, OpSize, TB, Requires<[FastBTMem]>;
|
||||
>, OpSize16, TB, Requires<[FastBTMem]>;
|
||||
def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
||||
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
||||
// [(X86bt (loadi32 addr:$src1), GR32:$src2),
|
||||
// (implicit EFLAGS)]
|
||||
[], IIC_BT_MR
|
||||
>, OpSize16, TB, Requires<[FastBTMem]>;
|
||||
>, OpSize32, TB, Requires<[FastBTMem]>;
|
||||
def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
||||
// [(X86bt (loadi64 addr:$src1), GR64:$src2),
|
||||
@ -1434,11 +1435,11 @@ let SchedRW = [WriteALU] in {
|
||||
def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
||||
"bt{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86bt GR16:$src1, i16immSExt8:$src2))],
|
||||
IIC_BT_RI>, OpSize, TB;
|
||||
IIC_BT_RI>, OpSize16, TB;
|
||||
def BT32ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
||||
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86bt GR32:$src1, i32immSExt8:$src2))],
|
||||
IIC_BT_RI>, OpSize16, TB;
|
||||
IIC_BT_RI>, OpSize32, TB;
|
||||
def BT64ri8 : RIi8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86bt GR64:$src1, i64immSExt8:$src2))],
|
||||
@ -1452,11 +1453,11 @@ let SchedRW = [WriteALU] in {
|
||||
def BT16mi8 : Ii8<0xBA, MRM4m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
||||
"bt{w}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86bt (loadi16 addr:$src1), i16immSExt8:$src2))
|
||||
], IIC_BT_MI>, OpSize, TB;
|
||||
], IIC_BT_MI>, OpSize16, TB;
|
||||
def BT32mi8 : Ii8<0xBA, MRM4m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
||||
"bt{l}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86bt (loadi32 addr:$src1), i32immSExt8:$src2))
|
||||
], IIC_BT_MI>, OpSize16, TB;
|
||||
], IIC_BT_MI>, OpSize32, TB;
|
||||
def BT64mi8 : RIi8<0xBA, MRM4m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
"bt{q}\t{$src2, $src1|$src1, $src2}",
|
||||
[(set EFLAGS, (X86bt (loadi64 addr:$src1),
|
||||
@ -1467,10 +1468,10 @@ let hasSideEffects = 0 in {
|
||||
let SchedRW = [WriteALU] in {
|
||||
def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
||||
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
||||
"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
|
||||
} // SchedRW
|
||||
@ -1478,10 +1479,10 @@ def BTC64rr : RI<0xBB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def BTC16mr : I<0xBB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
||||
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTC32mr : I<0xBB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
||||
"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
|
||||
}
|
||||
@ -1489,10 +1490,10 @@ def BTC64mr : RI<0xBB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
let SchedRW = [WriteALU] in {
|
||||
def BTC16ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
||||
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTC32ri8 : Ii8<0xBA, MRM7r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
||||
"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
|
||||
} // SchedRW
|
||||
@ -1500,10 +1501,10 @@ def BTC64ri8 : RIi8<0xBA, MRM7r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def BTC16mi8 : Ii8<0xBA, MRM7m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
||||
"btc{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTC32mi8 : Ii8<0xBA, MRM7m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
||||
"btc{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
"btc{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
|
||||
}
|
||||
@ -1511,10 +1512,10 @@ def BTC64mi8 : RIi8<0xBA, MRM7m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
let SchedRW = [WriteALU] in {
|
||||
def BTR16rr : I<0xB3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
||||
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTR32rr : I<0xB3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
||||
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"btr{q}\t{$src2, $src1|$src1, $src2}", []>, TB;
|
||||
} // SchedRW
|
||||
@ -1522,10 +1523,10 @@ def BTR64rr : RI<0xB3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def BTR16mr : I<0xB3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
||||
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTR32mr : I<0xB3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
||||
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
|
||||
}
|
||||
@ -1533,10 +1534,10 @@ def BTR64mr : RI<0xB3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
let SchedRW = [WriteALU] in {
|
||||
def BTR16ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
||||
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTR32ri8 : Ii8<0xBA, MRM6r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
||||
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
|
||||
} // SchedRW
|
||||
@ -1544,10 +1545,10 @@ def BTR64ri8 : RIi8<0xBA, MRM6r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def BTR16mi8 : Ii8<0xBA, MRM6m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
||||
"btr{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTR32mi8 : Ii8<0xBA, MRM6m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
||||
"btr{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
"btr{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
|
||||
}
|
||||
@ -1555,21 +1556,21 @@ def BTR64mi8 : RIi8<0xBA, MRM6m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
let SchedRW = [WriteALU] in {
|
||||
def BTS16rr : I<0xAB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
|
||||
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTS32rr : I<0xAB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
|
||||
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTS64rr : RI<0xAB, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
|
||||
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
|
||||
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RR>, TB;
|
||||
} // SchedRW
|
||||
|
||||
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def BTS16mr : I<0xAB, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
|
||||
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
|
||||
OpSize, TB;
|
||||
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
|
||||
OpSize16, TB;
|
||||
def BTS32mr : I<0xAB, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
|
||||
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
|
||||
OpSize16, TB;
|
||||
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>,
|
||||
OpSize32, TB;
|
||||
def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MR>, TB;
|
||||
}
|
||||
@ -1577,10 +1578,10 @@ def BTS64mr : RI<0xAB, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
|
||||
let SchedRW = [WriteALU] in {
|
||||
def BTS16ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR16:$src1, i16i8imm:$src2),
|
||||
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTS32ri8 : Ii8<0xBA, MRM5r, (outs), (ins GR32:$src1, i32i8imm:$src2),
|
||||
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_RI>, TB;
|
||||
} // SchedRW
|
||||
@ -1588,10 +1589,10 @@ def BTS64ri8 : RIi8<0xBA, MRM5r, (outs), (ins GR64:$src1, i64i8imm:$src2),
|
||||
let mayLoad = 1, mayStore = 1, SchedRW = [WriteALULd, WriteRMW] in {
|
||||
def BTS16mi8 : Ii8<0xBA, MRM5m, (outs), (ins i16mem:$src1, i16i8imm:$src2),
|
||||
"bts{w}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
|
||||
OpSize, TB;
|
||||
OpSize16, TB;
|
||||
def BTS32mi8 : Ii8<0xBA, MRM5m, (outs), (ins i32mem:$src1, i32i8imm:$src2),
|
||||
"bts{l}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>,
|
||||
OpSize16, TB;
|
||||
OpSize32, TB;
|
||||
def BTS64mi8 : RIi8<0xBA, MRM5m, (outs), (ins i64mem:$src1, i64i8imm:$src2),
|
||||
"bts{q}\t{$src2, $src1|$src1, $src2}", [], IIC_BTX_MI>, TB;
|
||||
}
|
||||
@ -1621,14 +1622,14 @@ multiclass ATOMIC_SWAP<bits<8> opc8, bits<8> opc, string mnemonic, string frag,
|
||||
[(set
|
||||
GR16:$dst,
|
||||
(!cast<PatFrag>(frag # "_16") addr:$ptr, GR16:$val))],
|
||||
itin>, OpSize;
|
||||
itin>, OpSize16;
|
||||
def NAME#32rm : I<opc, MRMSrcMem, (outs GR32:$dst),
|
||||
(ins GR32:$val, i32mem:$ptr),
|
||||
!strconcat(mnemonic, "{l}\t{$val, $ptr|$ptr, $val}"),
|
||||
[(set
|
||||
GR32:$dst,
|
||||
(!cast<PatFrag>(frag # "_32") addr:$ptr, GR32:$val))],
|
||||
itin>, OpSize16;
|
||||
itin>, OpSize32;
|
||||
def NAME#64rm : RI<opc, MRMSrcMem, (outs GR64:$dst),
|
||||
(ins GR64:$val, i64mem:$ptr),
|
||||
!strconcat(mnemonic, "{q}\t{$val, $ptr|$ptr, $val}"),
|
||||
@ -1647,20 +1648,21 @@ let Constraints = "$val = $dst" in {
|
||||
def XCHG8rr : I<0x86, MRMSrcReg, (outs GR8:$dst), (ins GR8:$val, GR8:$src),
|
||||
"xchg{b}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
|
||||
def XCHG16rr : I<0x87, MRMSrcReg, (outs GR16:$dst), (ins GR16:$val, GR16:$src),
|
||||
"xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>, OpSize;
|
||||
"xchg{w}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
|
||||
OpSize16;
|
||||
def XCHG32rr : I<0x87, MRMSrcReg, (outs GR32:$dst), (ins GR32:$val, GR32:$src),
|
||||
"xchg{l}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def XCHG64rr : RI<0x87, MRMSrcReg, (outs GR64:$dst), (ins GR64:$val,GR64:$src),
|
||||
"xchg{q}\t{$val, $src|$src, $val}", [], IIC_XCHG_REG>;
|
||||
}
|
||||
|
||||
// Swap between EAX and other registers.
|
||||
def XCHG16ar : I<0x90, AddRegFrm, (outs), (ins GR16:$src),
|
||||
"xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize;
|
||||
"xchg{w}\t{$src, %ax|ax, $src}", [], IIC_XCHG_REG>, OpSize16;
|
||||
def XCHG32ar : I<0x90, AddRegFrm, (outs), (ins GR32:$src),
|
||||
"xchg{l}\t{$src, %eax|eax, $src}", [], IIC_XCHG_REG>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
// Uses GR32_NOAX in 64-bit mode to prevent encoding using the 0x90 NOP encoding.
|
||||
// xchg %eax, %eax needs to clear upper 32-bits of RAX so is not a NOP.
|
||||
def XCHG32ar64 : I<0x90, AddRegFrm, (outs), (ins GR32_NOAX:$src),
|
||||
@ -1675,10 +1677,10 @@ def XADD8rr : I<0xC0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
|
||||
"xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
|
||||
def XADD16rr : I<0xC1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
|
||||
OpSize;
|
||||
OpSize16;
|
||||
def XADD32rr : I<0xC1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def XADD64rr : RI<0xC1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
||||
"xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_REG>, TB;
|
||||
} // SchedRW
|
||||
@ -1688,10 +1690,10 @@ def XADD8rm : I<0xC0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
|
||||
"xadd{b}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
|
||||
def XADD16rm : I<0xC1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
||||
"xadd{w}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
|
||||
OpSize;
|
||||
OpSize16;
|
||||
def XADD32rm : I<0xC1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
||||
"xadd{l}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def XADD64rm : RI<0xC1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
||||
"xadd{q}\t{$src, $dst|$dst, $src}", [], IIC_XADD_MEM>, TB;
|
||||
|
||||
@ -1703,10 +1705,10 @@ def CMPXCHG8rr : I<0xB0, MRMDestReg, (outs GR8:$dst), (ins GR8:$src),
|
||||
IIC_CMPXCHG_REG8>, TB;
|
||||
def CMPXCHG16rr : I<0xB1, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
|
||||
IIC_CMPXCHG_REG>, TB, OpSize;
|
||||
IIC_CMPXCHG_REG>, TB, OpSize16;
|
||||
def CMPXCHG32rr : I<0xB1, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
|
||||
IIC_CMPXCHG_REG>, TB, OpSize16;
|
||||
IIC_CMPXCHG_REG>, TB, OpSize32;
|
||||
def CMPXCHG64rr : RI<0xB1, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
|
||||
"cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
|
||||
IIC_CMPXCHG_REG>, TB;
|
||||
@ -1719,10 +1721,10 @@ def CMPXCHG8rm : I<0xB0, MRMDestMem, (outs), (ins i8mem:$dst, GR8:$src),
|
||||
IIC_CMPXCHG_MEM8>, TB;
|
||||
def CMPXCHG16rm : I<0xB1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
||||
"cmpxchg{w}\t{$src, $dst|$dst, $src}", [],
|
||||
IIC_CMPXCHG_MEM>, TB, OpSize;
|
||||
IIC_CMPXCHG_MEM>, TB, OpSize16;
|
||||
def CMPXCHG32rm : I<0xB1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
||||
"cmpxchg{l}\t{$src, $dst|$dst, $src}", [],
|
||||
IIC_CMPXCHG_MEM>, TB, OpSize16;
|
||||
IIC_CMPXCHG_MEM>, TB, OpSize32;
|
||||
def CMPXCHG64rm : RI<0xB1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
||||
"cmpxchg{q}\t{$src, $dst|$dst, $src}", [],
|
||||
IIC_CMPXCHG_MEM>, TB;
|
||||
@ -1764,9 +1766,9 @@ let SchedRW = [WriteMicrocoded] in {
|
||||
def LODSB : I<0xAC, RawFrmSrc, (outs), (ins srcidx8:$src),
|
||||
"lodsb\t{$src, %al|al, $src}", [], IIC_LODS>;
|
||||
def LODSW : I<0xAD, RawFrmSrc, (outs), (ins srcidx16:$src),
|
||||
"lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize;
|
||||
"lodsw\t{$src, %ax|ax, $src}", [], IIC_LODS>, OpSize16;
|
||||
def LODSL : I<0xAD, RawFrmSrc, (outs), (ins srcidx32:$src),
|
||||
"lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize16;
|
||||
"lods{l|d}\t{$src, %eax|eax, $src}", [], IIC_LODS>, OpSize32;
|
||||
def LODSQ : RI<0xAD, RawFrmSrc, (outs), (ins srcidx64:$src),
|
||||
"lodsq\t{$src, %rax|rax, $src}", [], IIC_LODS>;
|
||||
}
|
||||
@ -1775,9 +1777,9 @@ let SchedRW = [WriteSystem] in {
|
||||
def OUTSB : I<0x6E, RawFrmSrc, (outs), (ins srcidx8:$src),
|
||||
"outsb\t{$src, %dx|dx, $src}", [], IIC_OUTS>;
|
||||
def OUTSW : I<0x6F, RawFrmSrc, (outs), (ins srcidx16:$src),
|
||||
"outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize;
|
||||
"outsw\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
|
||||
def OUTSL : I<0x6F, RawFrmSrc, (outs), (ins srcidx32:$src),
|
||||
"outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize16;
|
||||
"outs{l|d}\t{$src, %dx|dx, $src}", [], IIC_OUTS>, OpSize32;
|
||||
}
|
||||
|
||||
// Flag instructions
|
||||
@ -1832,10 +1834,10 @@ def DAS : I<0x2F, RawFrm, (outs), (ins), "das", [], IIC_DAS>,
|
||||
let SchedRW = [WriteSystem] in {
|
||||
// Check Array Index Against Bounds
|
||||
def BOUNDS16rm : I<0x62, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize,
|
||||
"bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
|
||||
Requires<[Not64BitMode]>;
|
||||
def BOUNDS32rm : I<0x62, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||
"bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize16,
|
||||
"bound\t{$src, $dst|$dst, $src}", [], IIC_BOUND>, OpSize32,
|
||||
Requires<[Not64BitMode]>;
|
||||
|
||||
// Adjust RPL Field of Segment Selector
|
||||
@ -1855,11 +1857,11 @@ let Predicates = [HasMOVBE] in {
|
||||
def MOVBE16rm : I<0xF0, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"movbe{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, (bswap (loadi16 addr:$src)))], IIC_MOVBE>,
|
||||
OpSize, T8;
|
||||
OpSize16, T8;
|
||||
def MOVBE32rm : I<0xF0, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||
"movbe{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (bswap (loadi32 addr:$src)))], IIC_MOVBE>,
|
||||
OpSize16, T8;
|
||||
OpSize32, T8;
|
||||
def MOVBE64rm : RI<0xF0, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
||||
"movbe{q}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR64:$dst, (bswap (loadi64 addr:$src)))], IIC_MOVBE>,
|
||||
@ -1869,11 +1871,11 @@ let Predicates = [HasMOVBE] in {
|
||||
def MOVBE16mr : I<0xF1, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),
|
||||
"movbe{w}\t{$src, $dst|$dst, $src}",
|
||||
[(store (bswap GR16:$src), addr:$dst)], IIC_MOVBE>,
|
||||
OpSize, T8;
|
||||
OpSize16, T8;
|
||||
def MOVBE32mr : I<0xF1, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src),
|
||||
"movbe{l}\t{$src, $dst|$dst, $src}",
|
||||
[(store (bswap GR32:$src), addr:$dst)], IIC_MOVBE>,
|
||||
OpSize16, T8;
|
||||
OpSize32, T8;
|
||||
def MOVBE64mr : RI<0xF1, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src),
|
||||
"movbe{q}\t{$src, $dst|$dst, $src}",
|
||||
[(store (bswap GR64:$src), addr:$dst)], IIC_MOVBE>,
|
||||
@ -1887,10 +1889,10 @@ let Predicates = [HasMOVBE] in {
|
||||
let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
|
||||
def RDRAND16r : I<0xC7, MRM6r, (outs GR16:$dst), (ins),
|
||||
"rdrand{w}\t$dst",
|
||||
[(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize, TB;
|
||||
[(set GR16:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
|
||||
def RDRAND32r : I<0xC7, MRM6r, (outs GR32:$dst), (ins),
|
||||
"rdrand{l}\t$dst",
|
||||
[(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize16, TB;
|
||||
[(set GR32:$dst, EFLAGS, (X86rdrand))]>, OpSize32, TB;
|
||||
def RDRAND64r : RI<0xC7, MRM6r, (outs GR64:$dst), (ins),
|
||||
"rdrand{q}\t$dst",
|
||||
[(set GR64:$dst, EFLAGS, (X86rdrand))]>, TB;
|
||||
@ -1902,10 +1904,10 @@ let Predicates = [HasRDRAND], Defs = [EFLAGS] in {
|
||||
let Predicates = [HasRDSEED], Defs = [EFLAGS] in {
|
||||
def RDSEED16r : I<0xC7, MRM7r, (outs GR16:$dst), (ins),
|
||||
"rdseed{w}\t$dst",
|
||||
[(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize, TB;
|
||||
[(set GR16:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
|
||||
def RDSEED32r : I<0xC7, MRM7r, (outs GR32:$dst), (ins),
|
||||
"rdseed{l}\t$dst",
|
||||
[(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize16, TB;
|
||||
[(set GR32:$dst, EFLAGS, (X86rdseed))]>, OpSize32, TB;
|
||||
def RDSEED64r : RI<0xC7, MRM7r, (outs GR64:$dst), (ins),
|
||||
"rdseed{q}\t$dst",
|
||||
[(set GR64:$dst, EFLAGS, (X86rdseed))]>, TB;
|
||||
@ -1918,20 +1920,20 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
|
||||
def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"lzcnt{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, XS,
|
||||
OpSize;
|
||||
OpSize16;
|
||||
def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"lzcnt{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, (ctlz (loadi16 addr:$src))),
|
||||
(implicit EFLAGS)]>, XS, OpSize;
|
||||
(implicit EFLAGS)]>, XS, OpSize16;
|
||||
|
||||
def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"lzcnt{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, XS,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||
"lzcnt{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (ctlz (loadi32 addr:$src))),
|
||||
(implicit EFLAGS)]>, XS, OpSize16;
|
||||
(implicit EFLAGS)]>, XS, OpSize32;
|
||||
|
||||
def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
||||
"lzcnt{q}\t{$src, $dst|$dst, $src}",
|
||||
@ -1950,20 +1952,20 @@ let Predicates = [HasBMI], Defs = [EFLAGS] in {
|
||||
def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"tzcnt{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, XS,
|
||||
OpSize;
|
||||
OpSize16;
|
||||
def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"tzcnt{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, (cttz (loadi16 addr:$src))),
|
||||
(implicit EFLAGS)]>, XS, OpSize;
|
||||
(implicit EFLAGS)]>, XS, OpSize16;
|
||||
|
||||
def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"tzcnt{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, XS,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||
"tzcnt{l}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR32:$dst, (cttz (loadi32 addr:$src))),
|
||||
(implicit EFLAGS)]>, XS, OpSize16;
|
||||
(implicit EFLAGS)]>, XS, OpSize32;
|
||||
|
||||
def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
||||
"tzcnt{q}\t{$src, $dst|$dst, $src}",
|
||||
|
||||
@ -6789,11 +6789,11 @@ let Defs = [EFLAGS], Predicates = [HasPOPCNT] in {
|
||||
"popcnt{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)],
|
||||
IIC_SSE_POPCNT_RR>,
|
||||
OpSize, XS;
|
||||
OpSize16, XS;
|
||||
def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"popcnt{w}\t{$src, $dst|$dst, $src}",
|
||||
[(set GR16:$dst, (ctpop (loadi16 addr:$src))),
|
||||
(implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize, XS;
|
||||
(implicit EFLAGS)], IIC_SSE_POPCNT_RM>, OpSize16, XS;
|
||||
|
||||
def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"popcnt{l}\t{$src, $dst|$dst, $src}",
|
||||
@ -7478,13 +7478,13 @@ let Constraints = "$src1 = $dst" in {
|
||||
def CRC32r32r8 : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
|
||||
int_x86_sse42_crc32_32_8>;
|
||||
def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
|
||||
int_x86_sse42_crc32_32_16>, OpSize;
|
||||
int_x86_sse42_crc32_32_16>, OpSize16;
|
||||
def CRC32r32r16 : SS42I_crc32r<0xF1, "crc32{w}", GR32, GR16,
|
||||
int_x86_sse42_crc32_32_16>, OpSize;
|
||||
int_x86_sse42_crc32_32_16>, OpSize16;
|
||||
def CRC32r32m32 : SS42I_crc32m<0xF1, "crc32{l}", GR32, i32mem,
|
||||
int_x86_sse42_crc32_32_32>, OpSize16;
|
||||
int_x86_sse42_crc32_32_32>, OpSize32;
|
||||
def CRC32r32r32 : SS42I_crc32r<0xF1, "crc32{l}", GR32, GR32,
|
||||
int_x86_sse42_crc32_32_32>, OpSize16;
|
||||
int_x86_sse42_crc32_32_32>, OpSize32;
|
||||
def CRC32r64m64 : SS42I_crc32m<0xF1, "crc32{q}", GR64, i64mem,
|
||||
int_x86_sse42_crc32_64_64>, REX_W;
|
||||
def CRC32r64r64 : SS42I_crc32r<0xF1, "crc32{q}", GR64, GR64,
|
||||
|
||||
@ -22,10 +22,10 @@ def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
[(set GR8:$dst, (shl GR8:$src1, CL))], IIC_SR>;
|
||||
def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"shl{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize;
|
||||
[(set GR16:$dst, (shl GR16:$src1, CL))], IIC_SR>, OpSize16;
|
||||
def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"shl{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize16;
|
||||
[(set GR32:$dst, (shl GR32:$src1, CL))], IIC_SR>, OpSize32;
|
||||
def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"shl{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (shl GR64:$src1, CL))], IIC_SR>;
|
||||
@ -39,11 +39,11 @@ let isConvertibleToThreeAddress = 1 in { // Can transform into LEA.
|
||||
def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
||||
"shl{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))], IIC_SR>,
|
||||
OpSize;
|
||||
OpSize16;
|
||||
def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
||||
"shl{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (shl GR32:$src1, (i8 imm:$src2)))], IIC_SR>,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
|
||||
(ins GR64:$src1, i8imm:$src2),
|
||||
"shl{q}\t{$src2, $dst|$dst, $src2}",
|
||||
@ -56,9 +56,9 @@ let hasSideEffects = 0 in {
|
||||
def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
|
||||
"shl{b}\t$dst", [], IIC_SR>;
|
||||
def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"shl{w}\t$dst", [], IIC_SR>, OpSize;
|
||||
"shl{w}\t$dst", [], IIC_SR>, OpSize16;
|
||||
def SHL32r1 : I<0xD1, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"shl{l}\t$dst", [], IIC_SR>, OpSize16;
|
||||
"shl{l}\t$dst", [], IIC_SR>, OpSize32;
|
||||
def SHL64r1 : RI<0xD1, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"shl{q}\t$dst", [], IIC_SR>;
|
||||
} // hasSideEffects = 0
|
||||
@ -76,11 +76,11 @@ def SHL8mCL : I<0xD2, MRM4m, (outs), (ins i8mem :$dst),
|
||||
def SHL16mCL : I<0xD3, MRM4m, (outs), (ins i16mem:$dst),
|
||||
"shl{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (shl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
|
||||
OpSize;
|
||||
OpSize16;
|
||||
def SHL32mCL : I<0xD3, MRM4m, (outs), (ins i32mem:$dst),
|
||||
"shl{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (shl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def SHL64mCL : RI<0xD3, MRM4m, (outs), (ins i64mem:$dst),
|
||||
"shl{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (shl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
|
||||
@ -92,12 +92,11 @@ def SHL8mi : Ii8<0xC0, MRM4m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||
def SHL16mi : Ii8<0xC1, MRM4m, (outs), (ins i16mem:$dst, i8imm:$src),
|
||||
"shl{w}\t{$src, $dst|$dst, $src}",
|
||||
[(store (shl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SHL32mi : Ii8<0xC1, MRM4m, (outs), (ins i32mem:$dst, i8imm:$src),
|
||||
"shl{l}\t{$src, $dst|$dst, $src}",
|
||||
[(store (shl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SHL64mi : RIi8<0xC1, MRM4m, (outs), (ins i64mem:$dst, i8imm:$src),
|
||||
"shl{q}\t{$src, $dst|$dst, $src}",
|
||||
[(store (shl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
@ -111,12 +110,11 @@ def SHL8m1 : I<0xD0, MRM4m, (outs), (ins i8mem :$dst),
|
||||
def SHL16m1 : I<0xD1, MRM4m, (outs), (ins i16mem:$dst),
|
||||
"shl{w}\t$dst",
|
||||
[(store (shl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SHL32m1 : I<0xD1, MRM4m, (outs), (ins i32mem:$dst),
|
||||
"shl{l}\t$dst",
|
||||
[(store (shl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SHL64m1 : RI<0xD1, MRM4m, (outs), (ins i64mem:$dst),
|
||||
"shl{q}\t$dst",
|
||||
[(store (shl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
|
||||
@ -130,10 +128,10 @@ def SHR8rCL : I<0xD2, MRM5r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
[(set GR8:$dst, (srl GR8:$src1, CL))], IIC_SR>;
|
||||
def SHR16rCL : I<0xD3, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"shr{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize;
|
||||
[(set GR16:$dst, (srl GR16:$src1, CL))], IIC_SR>, OpSize16;
|
||||
def SHR32rCL : I<0xD3, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"shr{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize16;
|
||||
[(set GR32:$dst, (srl GR32:$src1, CL))], IIC_SR>, OpSize32;
|
||||
def SHR64rCL : RI<0xD3, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"shr{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (srl GR64:$src1, CL))], IIC_SR>;
|
||||
@ -145,11 +143,11 @@ def SHR8ri : Ii8<0xC0, MRM5r, (outs GR8:$dst), (ins GR8:$src1, i8imm:$src2),
|
||||
def SHR16ri : Ii8<0xC1, MRM5r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
||||
"shr{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))],
|
||||
IIC_SR>, OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SHR32ri : Ii8<0xC1, MRM5r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
||||
"shr{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (srl GR32:$src1, (i8 imm:$src2)))],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SHR64ri : RIi8<0xC1, MRM5r, (outs GR64:$dst), (ins GR64:$src1, i8imm:$src2),
|
||||
"shr{q}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR64:$dst, (srl GR64:$src1, (i8 imm:$src2)))], IIC_SR>;
|
||||
@ -160,10 +158,10 @@ def SHR8r1 : I<0xD0, MRM5r, (outs GR8:$dst), (ins GR8:$src1),
|
||||
[(set GR8:$dst, (srl GR8:$src1, (i8 1)))], IIC_SR>;
|
||||
def SHR16r1 : I<0xD1, MRM5r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"shr{w}\t$dst",
|
||||
[(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize;
|
||||
[(set GR16:$dst, (srl GR16:$src1, (i8 1)))], IIC_SR>, OpSize16;
|
||||
def SHR32r1 : I<0xD1, MRM5r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"shr{l}\t$dst",
|
||||
[(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize16;
|
||||
[(set GR32:$dst, (srl GR32:$src1, (i8 1)))], IIC_SR>, OpSize32;
|
||||
def SHR64r1 : RI<0xD1, MRM5r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"shr{q}\t$dst",
|
||||
[(set GR64:$dst, (srl GR64:$src1, (i8 1)))], IIC_SR>;
|
||||
@ -178,11 +176,11 @@ def SHR8mCL : I<0xD2, MRM5m, (outs), (ins i8mem :$dst),
|
||||
def SHR16mCL : I<0xD3, MRM5m, (outs), (ins i16mem:$dst),
|
||||
"shr{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (srl (loadi16 addr:$dst), CL), addr:$dst)], IIC_SR>,
|
||||
OpSize;
|
||||
OpSize16;
|
||||
def SHR32mCL : I<0xD3, MRM5m, (outs), (ins i32mem:$dst),
|
||||
"shr{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (srl (loadi32 addr:$dst), CL), addr:$dst)], IIC_SR>,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def SHR64mCL : RI<0xD3, MRM5m, (outs), (ins i64mem:$dst),
|
||||
"shr{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (srl (loadi64 addr:$dst), CL), addr:$dst)], IIC_SR>;
|
||||
@ -194,12 +192,11 @@ def SHR8mi : Ii8<0xC0, MRM5m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||
def SHR16mi : Ii8<0xC1, MRM5m, (outs), (ins i16mem:$dst, i8imm:$src),
|
||||
"shr{w}\t{$src, $dst|$dst, $src}",
|
||||
[(store (srl (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SHR32mi : Ii8<0xC1, MRM5m, (outs), (ins i32mem:$dst, i8imm:$src),
|
||||
"shr{l}\t{$src, $dst|$dst, $src}",
|
||||
[(store (srl (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SHR64mi : RIi8<0xC1, MRM5m, (outs), (ins i64mem:$dst, i8imm:$src),
|
||||
"shr{q}\t{$src, $dst|$dst, $src}",
|
||||
[(store (srl (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
@ -213,11 +210,11 @@ def SHR8m1 : I<0xD0, MRM5m, (outs), (ins i8mem :$dst),
|
||||
def SHR16m1 : I<0xD1, MRM5m, (outs), (ins i16mem:$dst),
|
||||
"shr{w}\t$dst",
|
||||
[(store (srl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>,OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SHR32m1 : I<0xD1, MRM5m, (outs), (ins i32mem:$dst),
|
||||
"shr{l}\t$dst",
|
||||
[(store (srl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SHR64m1 : RI<0xD1, MRM5m, (outs), (ins i64mem:$dst),
|
||||
"shr{q}\t$dst",
|
||||
[(store (srl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
|
||||
@ -233,11 +230,11 @@ def SAR8rCL : I<0xD2, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
def SAR16rCL : I<0xD3, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"sar{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (sra GR16:$src1, CL))],
|
||||
IIC_SR>, OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SAR32rCL : I<0xD3, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"sar{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (sra GR32:$src1, CL))],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SAR64rCL : RI<0xD3, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"sar{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (sra GR64:$src1, CL))],
|
||||
@ -251,12 +248,11 @@ def SAR8ri : Ii8<0xC0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
||||
def SAR16ri : Ii8<0xC1, MRM7r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
||||
"sar{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (sra GR16:$src1, (i8 imm:$src2)))],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SAR32ri : Ii8<0xC1, MRM7r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
||||
"sar{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (sra GR32:$src1, (i8 imm:$src2)))],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SAR64ri : RIi8<0xC1, MRM7r, (outs GR64:$dst),
|
||||
(ins GR64:$src1, i8imm:$src2),
|
||||
"sar{q}\t{$src2, $dst|$dst, $src2}",
|
||||
@ -271,11 +267,11 @@ def SAR8r1 : I<0xD0, MRM7r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
def SAR16r1 : I<0xD1, MRM7r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"sar{w}\t$dst",
|
||||
[(set GR16:$dst, (sra GR16:$src1, (i8 1)))],
|
||||
IIC_SR>, OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SAR32r1 : I<0xD1, MRM7r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"sar{l}\t$dst",
|
||||
[(set GR32:$dst, (sra GR32:$src1, (i8 1)))],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SAR64r1 : RI<0xD1, MRM7r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"sar{q}\t$dst",
|
||||
[(set GR64:$dst, (sra GR64:$src1, (i8 1)))],
|
||||
@ -292,11 +288,11 @@ def SAR8mCL : I<0xD2, MRM7m, (outs), (ins i8mem :$dst),
|
||||
def SAR16mCL : I<0xD3, MRM7m, (outs), (ins i16mem:$dst),
|
||||
"sar{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (sra (loadi16 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>, OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SAR32mCL : I<0xD3, MRM7m, (outs), (ins i32mem:$dst),
|
||||
"sar{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (sra (loadi32 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SAR64mCL : RI<0xD3, MRM7m, (outs), (ins i64mem:$dst),
|
||||
"sar{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (sra (loadi64 addr:$dst), CL), addr:$dst)],
|
||||
@ -309,12 +305,11 @@ def SAR8mi : Ii8<0xC0, MRM7m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||
def SAR16mi : Ii8<0xC1, MRM7m, (outs), (ins i16mem:$dst, i8imm:$src),
|
||||
"sar{w}\t{$src, $dst|$dst, $src}",
|
||||
[(store (sra (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SAR32mi : Ii8<0xC1, MRM7m, (outs), (ins i32mem:$dst, i8imm:$src),
|
||||
"sar{l}\t{$src, $dst|$dst, $src}",
|
||||
[(store (sra (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SAR64mi : RIi8<0xC1, MRM7m, (outs), (ins i64mem:$dst, i8imm:$src),
|
||||
"sar{q}\t{$src, $dst|$dst, $src}",
|
||||
[(store (sra (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
@ -328,12 +323,11 @@ def SAR8m1 : I<0xD0, MRM7m, (outs), (ins i8mem :$dst),
|
||||
def SAR16m1 : I<0xD1, MRM7m, (outs), (ins i16mem:$dst),
|
||||
"sar{w}\t$dst",
|
||||
[(store (sra (loadi16 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def SAR32m1 : I<0xD1, MRM7m, (outs), (ins i32mem:$dst),
|
||||
"sar{l}\t$dst",
|
||||
[(store (sra (loadi32 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def SAR64m1 : RI<0xD1, MRM7m, (outs), (ins i64mem:$dst),
|
||||
"sar{q}\t$dst",
|
||||
[(store (sra (loadi64 addr:$dst), (i8 1)), addr:$dst)],
|
||||
@ -355,20 +349,20 @@ def RCL8rCL : I<0xD2, MRM2r, (outs GR8:$dst), (ins GR8:$src1),
|
||||
"rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
def RCL16r1 : I<0xD1, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rcl{w}\t$dst", [], IIC_SR>, OpSize;
|
||||
"rcl{w}\t$dst", [], IIC_SR>, OpSize16;
|
||||
def RCL16ri : Ii8<0xC1, MRM2r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
||||
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
|
||||
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
|
||||
let Uses = [CL] in
|
||||
def RCL16rCL : I<0xD3, MRM2r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
|
||||
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
|
||||
|
||||
def RCL32r1 : I<0xD1, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rcl{l}\t$dst", [], IIC_SR>, OpSize16;
|
||||
"rcl{l}\t$dst", [], IIC_SR>, OpSize32;
|
||||
def RCL32ri : Ii8<0xC1, MRM2r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
||||
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
|
||||
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
|
||||
let Uses = [CL] in
|
||||
def RCL32rCL : I<0xD3, MRM2r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
|
||||
"rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
|
||||
|
||||
|
||||
def RCL64r1 : RI<0xD1, MRM2r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
@ -389,20 +383,20 @@ def RCR8rCL : I<0xD2, MRM3r, (outs GR8:$dst), (ins GR8:$src1),
|
||||
"rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
def RCR16r1 : I<0xD1, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rcr{w}\t$dst", [], IIC_SR>, OpSize;
|
||||
"rcr{w}\t$dst", [], IIC_SR>, OpSize16;
|
||||
def RCR16ri : Ii8<0xC1, MRM3r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$cnt),
|
||||
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
|
||||
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
|
||||
let Uses = [CL] in
|
||||
def RCR16rCL : I<0xD3, MRM3r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
|
||||
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
|
||||
|
||||
def RCR32r1 : I<0xD1, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rcr{l}\t$dst", [], IIC_SR>, OpSize16;
|
||||
"rcr{l}\t$dst", [], IIC_SR>, OpSize32;
|
||||
def RCR32ri : Ii8<0xC1, MRM3r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$cnt),
|
||||
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
|
||||
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
|
||||
let Uses = [CL] in
|
||||
def RCR32rCL : I<0xD3, MRM3r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
|
||||
"rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
|
||||
|
||||
def RCR64r1 : RI<0xD1, MRM3r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"rcr{q}\t$dst", [], IIC_SR>;
|
||||
@ -420,13 +414,13 @@ def RCL8m1 : I<0xD0, MRM2m, (outs), (ins i8mem:$dst),
|
||||
def RCL8mi : Ii8<0xC0, MRM2m, (outs), (ins i8mem:$dst, i8imm:$cnt),
|
||||
"rcl{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
|
||||
def RCL16m1 : I<0xD1, MRM2m, (outs), (ins i16mem:$dst),
|
||||
"rcl{w}\t$dst", [], IIC_SR>, OpSize;
|
||||
"rcl{w}\t$dst", [], IIC_SR>, OpSize16;
|
||||
def RCL16mi : Ii8<0xC1, MRM2m, (outs), (ins i16mem:$dst, i8imm:$cnt),
|
||||
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
|
||||
"rcl{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
|
||||
def RCL32m1 : I<0xD1, MRM2m, (outs), (ins i32mem:$dst),
|
||||
"rcl{l}\t$dst", [], IIC_SR>, OpSize16;
|
||||
"rcl{l}\t$dst", [], IIC_SR>, OpSize32;
|
||||
def RCL32mi : Ii8<0xC1, MRM2m, (outs), (ins i32mem:$dst, i8imm:$cnt),
|
||||
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
|
||||
"rcl{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
|
||||
def RCL64m1 : RI<0xD1, MRM2m, (outs), (ins i64mem:$dst),
|
||||
"rcl{q}\t$dst", [], IIC_SR>;
|
||||
def RCL64mi : RIi8<0xC1, MRM2m, (outs), (ins i64mem:$dst, i8imm:$cnt),
|
||||
@ -437,13 +431,13 @@ def RCR8m1 : I<0xD0, MRM3m, (outs), (ins i8mem:$dst),
|
||||
def RCR8mi : Ii8<0xC0, MRM3m, (outs), (ins i8mem:$dst, i8imm:$cnt),
|
||||
"rcr{b}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>;
|
||||
def RCR16m1 : I<0xD1, MRM3m, (outs), (ins i16mem:$dst),
|
||||
"rcr{w}\t$dst", [], IIC_SR>, OpSize;
|
||||
"rcr{w}\t$dst", [], IIC_SR>, OpSize16;
|
||||
def RCR16mi : Ii8<0xC1, MRM3m, (outs), (ins i16mem:$dst, i8imm:$cnt),
|
||||
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize;
|
||||
"rcr{w}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
|
||||
def RCR32m1 : I<0xD1, MRM3m, (outs), (ins i32mem:$dst),
|
||||
"rcr{l}\t$dst", [], IIC_SR>, OpSize16;
|
||||
"rcr{l}\t$dst", [], IIC_SR>, OpSize32;
|
||||
def RCR32mi : Ii8<0xC1, MRM3m, (outs), (ins i32mem:$dst, i8imm:$cnt),
|
||||
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize16;
|
||||
"rcr{l}\t{$cnt, $dst|$dst, $cnt}", [], IIC_SR>, OpSize32;
|
||||
def RCR64m1 : RI<0xD1, MRM3m, (outs), (ins i64mem:$dst),
|
||||
"rcr{q}\t$dst", [], IIC_SR>;
|
||||
def RCR64mi : RIi8<0xC1, MRM3m, (outs), (ins i64mem:$dst, i8imm:$cnt),
|
||||
@ -453,18 +447,18 @@ let Uses = [CL] in {
|
||||
def RCL8mCL : I<0xD2, MRM2m, (outs), (ins i8mem:$dst),
|
||||
"rcl{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
def RCL16mCL : I<0xD3, MRM2m, (outs), (ins i16mem:$dst),
|
||||
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
|
||||
"rcl{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
|
||||
def RCL32mCL : I<0xD3, MRM2m, (outs), (ins i32mem:$dst),
|
||||
"rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
|
||||
"rcl{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
|
||||
def RCL64mCL : RI<0xD3, MRM2m, (outs), (ins i64mem:$dst),
|
||||
"rcl{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
|
||||
def RCR8mCL : I<0xD2, MRM3m, (outs), (ins i8mem:$dst),
|
||||
"rcr{b}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
def RCR16mCL : I<0xD3, MRM3m, (outs), (ins i16mem:$dst),
|
||||
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize;
|
||||
"rcr{w}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
|
||||
def RCR32mCL : I<0xD3, MRM3m, (outs), (ins i32mem:$dst),
|
||||
"rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize16;
|
||||
"rcr{l}\t{%cl, $dst|$dst, cl}", [], IIC_SR>, OpSize32;
|
||||
def RCR64mCL : RI<0xD3, MRM3m, (outs), (ins i64mem:$dst),
|
||||
"rcr{q}\t{%cl, $dst|$dst, cl}", [], IIC_SR>;
|
||||
}
|
||||
@ -479,10 +473,10 @@ def ROL8rCL : I<0xD2, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
[(set GR8:$dst, (rotl GR8:$src1, CL))], IIC_SR>;
|
||||
def ROL16rCL : I<0xD3, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rol{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize;
|
||||
[(set GR16:$dst, (rotl GR16:$src1, CL))], IIC_SR>, OpSize16;
|
||||
def ROL32rCL : I<0xD3, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rol{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize16;
|
||||
[(set GR32:$dst, (rotl GR32:$src1, CL))], IIC_SR>, OpSize32;
|
||||
def ROL64rCL : RI<0xD3, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"rol{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (rotl GR64:$src1, CL))], IIC_SR>;
|
||||
@ -494,12 +488,11 @@ def ROL8ri : Ii8<0xC0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
||||
def ROL16ri : Ii8<0xC1, MRM0r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
||||
"rol{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (rotl GR16:$src1, (i8 imm:$src2)))],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROL32ri : Ii8<0xC1, MRM0r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
||||
"rol{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (rotl GR32:$src1, (i8 imm:$src2)))],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROL64ri : RIi8<0xC1, MRM0r, (outs GR64:$dst),
|
||||
(ins GR64:$src1, i8imm:$src2),
|
||||
"rol{q}\t{$src2, $dst|$dst, $src2}",
|
||||
@ -514,11 +507,11 @@ def ROL8r1 : I<0xD0, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
def ROL16r1 : I<0xD1, MRM0r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"rol{w}\t$dst",
|
||||
[(set GR16:$dst, (rotl GR16:$src1, (i8 1)))],
|
||||
IIC_SR>, OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROL32r1 : I<0xD1, MRM0r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"rol{l}\t$dst",
|
||||
[(set GR32:$dst, (rotl GR32:$src1, (i8 1)))],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROL64r1 : RI<0xD1, MRM0r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"rol{q}\t$dst",
|
||||
[(set GR64:$dst, (rotl GR64:$src1, (i8 1)))],
|
||||
@ -534,11 +527,11 @@ def ROL8mCL : I<0xD2, MRM0m, (outs), (ins i8mem :$dst),
|
||||
def ROL16mCL : I<0xD3, MRM0m, (outs), (ins i16mem:$dst),
|
||||
"rol{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotl (loadi16 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>, OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROL32mCL : I<0xD3, MRM0m, (outs), (ins i32mem:$dst),
|
||||
"rol{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotl (loadi32 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROL64mCL : RI<0xD3, MRM0m, (outs), (ins i64mem:$dst),
|
||||
"rol{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotl (loadi64 addr:$dst), CL), addr:$dst)],
|
||||
@ -551,12 +544,11 @@ def ROL8mi : Ii8<0xC0, MRM0m, (outs), (ins i8mem :$dst, i8imm:$src1),
|
||||
def ROL16mi : Ii8<0xC1, MRM0m, (outs), (ins i16mem:$dst, i8imm:$src1),
|
||||
"rol{w}\t{$src1, $dst|$dst, $src1}",
|
||||
[(store (rotl (loadi16 addr:$dst), (i8 imm:$src1)), addr:$dst)],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROL32mi : Ii8<0xC1, MRM0m, (outs), (ins i32mem:$dst, i8imm:$src1),
|
||||
"rol{l}\t{$src1, $dst|$dst, $src1}",
|
||||
[(store (rotl (loadi32 addr:$dst), (i8 imm:$src1)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROL64mi : RIi8<0xC1, MRM0m, (outs), (ins i64mem:$dst, i8imm:$src1),
|
||||
"rol{q}\t{$src1, $dst|$dst, $src1}",
|
||||
[(store (rotl (loadi64 addr:$dst), (i8 imm:$src1)), addr:$dst)],
|
||||
@ -570,12 +562,11 @@ def ROL8m1 : I<0xD0, MRM0m, (outs), (ins i8mem :$dst),
|
||||
def ROL16m1 : I<0xD1, MRM0m, (outs), (ins i16mem:$dst),
|
||||
"rol{w}\t$dst",
|
||||
[(store (rotl (loadi16 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROL32m1 : I<0xD1, MRM0m, (outs), (ins i32mem:$dst),
|
||||
"rol{l}\t$dst",
|
||||
[(store (rotl (loadi32 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROL64m1 : RI<0xD1, MRM0m, (outs), (ins i64mem:$dst),
|
||||
"rol{q}\t$dst",
|
||||
[(store (rotl (loadi64 addr:$dst), (i8 1)), addr:$dst)],
|
||||
@ -589,10 +580,10 @@ def ROR8rCL : I<0xD2, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
[(set GR8:$dst, (rotr GR8:$src1, CL))], IIC_SR>;
|
||||
def ROR16rCL : I<0xD3, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"ror{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize;
|
||||
[(set GR16:$dst, (rotr GR16:$src1, CL))], IIC_SR>, OpSize16;
|
||||
def ROR32rCL : I<0xD3, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"ror{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize16;
|
||||
[(set GR32:$dst, (rotr GR32:$src1, CL))], IIC_SR>, OpSize32;
|
||||
def ROR64rCL : RI<0xD3, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"ror{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(set GR64:$dst, (rotr GR64:$src1, CL))], IIC_SR>;
|
||||
@ -604,12 +595,11 @@ def ROR8ri : Ii8<0xC0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1, i8imm:$src2),
|
||||
def ROR16ri : Ii8<0xC1, MRM1r, (outs GR16:$dst), (ins GR16:$src1, i8imm:$src2),
|
||||
"ror{w}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR16:$dst, (rotr GR16:$src1, (i8 imm:$src2)))],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROR32ri : Ii8<0xC1, MRM1r, (outs GR32:$dst), (ins GR32:$src1, i8imm:$src2),
|
||||
"ror{l}\t{$src2, $dst|$dst, $src2}",
|
||||
[(set GR32:$dst, (rotr GR32:$src1, (i8 imm:$src2)))],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROR64ri : RIi8<0xC1, MRM1r, (outs GR64:$dst),
|
||||
(ins GR64:$src1, i8imm:$src2),
|
||||
"ror{q}\t{$src2, $dst|$dst, $src2}",
|
||||
@ -624,11 +614,11 @@ def ROR8r1 : I<0xD0, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1),
|
||||
def ROR16r1 : I<0xD1, MRM1r, (outs GR16:$dst), (ins GR16:$src1),
|
||||
"ror{w}\t$dst",
|
||||
[(set GR16:$dst, (rotr GR16:$src1, (i8 1)))],
|
||||
IIC_SR>, OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROR32r1 : I<0xD1, MRM1r, (outs GR32:$dst), (ins GR32:$src1),
|
||||
"ror{l}\t$dst",
|
||||
[(set GR32:$dst, (rotr GR32:$src1, (i8 1)))],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROR64r1 : RI<0xD1, MRM1r, (outs GR64:$dst), (ins GR64:$src1),
|
||||
"ror{q}\t$dst",
|
||||
[(set GR64:$dst, (rotr GR64:$src1, (i8 1)))],
|
||||
@ -644,11 +634,11 @@ def ROR8mCL : I<0xD2, MRM1m, (outs), (ins i8mem :$dst),
|
||||
def ROR16mCL : I<0xD3, MRM1m, (outs), (ins i16mem:$dst),
|
||||
"ror{w}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotr (loadi16 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>, OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROR32mCL : I<0xD3, MRM1m, (outs), (ins i32mem:$dst),
|
||||
"ror{l}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotr (loadi32 addr:$dst), CL), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROR64mCL : RI<0xD3, MRM1m, (outs), (ins i64mem:$dst),
|
||||
"ror{q}\t{%cl, $dst|$dst, cl}",
|
||||
[(store (rotr (loadi64 addr:$dst), CL), addr:$dst)],
|
||||
@ -661,12 +651,11 @@ def ROR8mi : Ii8<0xC0, MRM1m, (outs), (ins i8mem :$dst, i8imm:$src),
|
||||
def ROR16mi : Ii8<0xC1, MRM1m, (outs), (ins i16mem:$dst, i8imm:$src),
|
||||
"ror{w}\t{$src, $dst|$dst, $src}",
|
||||
[(store (rotr (loadi16 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROR32mi : Ii8<0xC1, MRM1m, (outs), (ins i32mem:$dst, i8imm:$src),
|
||||
"ror{l}\t{$src, $dst|$dst, $src}",
|
||||
[(store (rotr (loadi32 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROR64mi : RIi8<0xC1, MRM1m, (outs), (ins i64mem:$dst, i8imm:$src),
|
||||
"ror{q}\t{$src, $dst|$dst, $src}",
|
||||
[(store (rotr (loadi64 addr:$dst), (i8 imm:$src)), addr:$dst)],
|
||||
@ -680,12 +669,11 @@ def ROR8m1 : I<0xD0, MRM1m, (outs), (ins i8mem :$dst),
|
||||
def ROR16m1 : I<0xD1, MRM1m, (outs), (ins i16mem:$dst),
|
||||
"ror{w}\t$dst",
|
||||
[(store (rotr (loadi16 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>,
|
||||
OpSize;
|
||||
IIC_SR>, OpSize16;
|
||||
def ROR32m1 : I<0xD1, MRM1m, (outs), (ins i32mem:$dst),
|
||||
"ror{l}\t$dst",
|
||||
[(store (rotr (loadi32 addr:$dst), (i8 1)), addr:$dst)],
|
||||
IIC_SR>, OpSize16;
|
||||
IIC_SR>, OpSize32;
|
||||
def ROR64m1 : RI<0xD1, MRM1m, (outs), (ins i64mem:$dst),
|
||||
"ror{q}\t$dst",
|
||||
[(store (rotr (loadi64 addr:$dst), (i8 1)), addr:$dst)],
|
||||
@ -705,23 +693,23 @@ def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
|
||||
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2, CL))],
|
||||
IIC_SHD16_REG_CL>,
|
||||
TB, OpSize;
|
||||
TB, OpSize16;
|
||||
def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
|
||||
(ins GR16:$src1, GR16:$src2),
|
||||
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2, CL))],
|
||||
IIC_SHD16_REG_CL>,
|
||||
TB, OpSize;
|
||||
TB, OpSize16;
|
||||
def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
|
||||
(ins GR32:$src1, GR32:$src2),
|
||||
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2, CL))],
|
||||
IIC_SHD32_REG_CL>, TB, OpSize16;
|
||||
IIC_SHD32_REG_CL>, TB, OpSize32;
|
||||
def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
|
||||
(ins GR32:$src1, GR32:$src2),
|
||||
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2, CL))],
|
||||
IIC_SHD32_REG_CL>, TB, OpSize16;
|
||||
IIC_SHD32_REG_CL>, TB, OpSize32;
|
||||
def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
|
||||
(ins GR64:$src1, GR64:$src2),
|
||||
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
@ -743,28 +731,28 @@ def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
|
||||
"shld{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(set GR16:$dst, (X86shld GR16:$src1, GR16:$src2,
|
||||
(i8 imm:$src3)))], IIC_SHD16_REG_IM>,
|
||||
TB, OpSize;
|
||||
TB, OpSize16;
|
||||
def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
|
||||
(outs GR16:$dst),
|
||||
(ins GR16:$src1, GR16:$src2, i8imm:$src3),
|
||||
"shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(set GR16:$dst, (X86shrd GR16:$src1, GR16:$src2,
|
||||
(i8 imm:$src3)))], IIC_SHD16_REG_IM>,
|
||||
TB, OpSize;
|
||||
TB, OpSize16;
|
||||
def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
|
||||
(outs GR32:$dst),
|
||||
(ins GR32:$src1, GR32:$src2, i8imm:$src3),
|
||||
"shld{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(set GR32:$dst, (X86shld GR32:$src1, GR32:$src2,
|
||||
(i8 imm:$src3)))], IIC_SHD32_REG_IM>,
|
||||
TB, OpSize16;
|
||||
TB, OpSize32;
|
||||
def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
|
||||
(outs GR32:$dst),
|
||||
(ins GR32:$src1, GR32:$src2, i8imm:$src3),
|
||||
"shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(set GR32:$dst, (X86shrd GR32:$src1, GR32:$src2,
|
||||
(i8 imm:$src3)))], IIC_SHD32_REG_IM>,
|
||||
TB, OpSize16;
|
||||
TB, OpSize32;
|
||||
def SHLD64rri8 : RIi8<0xA4, MRMDestReg,
|
||||
(outs GR64:$dst),
|
||||
(ins GR64:$src1, GR64:$src2, i8imm:$src3),
|
||||
@ -787,20 +775,20 @@ let Uses = [CL] in {
|
||||
def SHLD16mrCL : I<0xA5, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
||||
"shld{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shld (loadi16 addr:$dst), GR16:$src2, CL),
|
||||
addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
|
||||
addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
|
||||
def SHRD16mrCL : I<0xAD, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src2),
|
||||
"shrd{w}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shrd (loadi16 addr:$dst), GR16:$src2, CL),
|
||||
addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize;
|
||||
addr:$dst)], IIC_SHD16_MEM_CL>, TB, OpSize16;
|
||||
|
||||
def SHLD32mrCL : I<0xA5, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||
"shld{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shld (loadi32 addr:$dst), GR32:$src2, CL),
|
||||
addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
|
||||
addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
|
||||
def SHRD32mrCL : I<0xAD, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src2),
|
||||
"shrd{l}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
[(store (X86shrd (loadi32 addr:$dst), GR32:$src2, CL),
|
||||
addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize16;
|
||||
addr:$dst)], IIC_SHD32_MEM_CL>, TB, OpSize32;
|
||||
|
||||
def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
|
||||
"shld{q}\t{%cl, $src2, $dst|$dst, $src2, cl}",
|
||||
@ -818,14 +806,14 @@ def SHLD16mri8 : Ii8<0xA4, MRMDestMem,
|
||||
[(store (X86shld (loadi16 addr:$dst), GR16:$src2,
|
||||
(i8 imm:$src3)), addr:$dst)],
|
||||
IIC_SHD16_MEM_IM>,
|
||||
TB, OpSize;
|
||||
TB, OpSize16;
|
||||
def SHRD16mri8 : Ii8<0xAC, MRMDestMem,
|
||||
(outs), (ins i16mem:$dst, GR16:$src2, i8imm:$src3),
|
||||
"shrd{w}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(store (X86shrd (loadi16 addr:$dst), GR16:$src2,
|
||||
(i8 imm:$src3)), addr:$dst)],
|
||||
IIC_SHD16_MEM_IM>,
|
||||
TB, OpSize;
|
||||
TB, OpSize16;
|
||||
|
||||
def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
|
||||
(outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
|
||||
@ -833,14 +821,14 @@ def SHLD32mri8 : Ii8<0xA4, MRMDestMem,
|
||||
[(store (X86shld (loadi32 addr:$dst), GR32:$src2,
|
||||
(i8 imm:$src3)), addr:$dst)],
|
||||
IIC_SHD32_MEM_IM>,
|
||||
TB, OpSize16;
|
||||
TB, OpSize32;
|
||||
def SHRD32mri8 : Ii8<0xAC, MRMDestMem,
|
||||
(outs), (ins i32mem:$dst, GR32:$src2, i8imm:$src3),
|
||||
"shrd{l}\t{$src3, $src2, $dst|$dst, $src2, $src3}",
|
||||
[(store (X86shrd (loadi32 addr:$dst), GR32:$src2,
|
||||
(i8 imm:$src3)), addr:$dst)],
|
||||
IIC_SHD32_MEM_IM>,
|
||||
TB, OpSize16;
|
||||
TB, OpSize32;
|
||||
|
||||
def SHLD64mri8 : RIi8<0xA4, MRMDestMem,
|
||||
(outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
|
||||
|
||||
@ -64,9 +64,9 @@ def SYSEXIT : I<0x35, RawFrm, (outs), (ins), "sysexit{l}", [],
|
||||
def SYSEXIT64 :RI<0x35, RawFrm, (outs), (ins), "sysexit{q}", []>, TB,
|
||||
Requires<[In64BitMode]>;
|
||||
|
||||
def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize;
|
||||
def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iret{w}", [], IIC_IRET>, OpSize16;
|
||||
def IRET32 : I<0xcf, RawFrm, (outs), (ins), "iret{l|d}", [], IIC_IRET>,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def IRET64 : RI<0xcf, RawFrm, (outs), (ins), "iretq", [], IIC_IRET>,
|
||||
Requires<[In64BitMode]>;
|
||||
} // SchedRW
|
||||
@ -81,47 +81,47 @@ def IN8rr : I<0xEC, RawFrm, (outs), (ins),
|
||||
"in{b}\t{%dx, %al|al, dx}", [], IIC_IN_RR>;
|
||||
let Defs = [AX], Uses = [DX] in
|
||||
def IN16rr : I<0xED, RawFrm, (outs), (ins),
|
||||
"in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize;
|
||||
"in{w}\t{%dx, %ax|ax, dx}", [], IIC_IN_RR>, OpSize16;
|
||||
let Defs = [EAX], Uses = [DX] in
|
||||
def IN32rr : I<0xED, RawFrm, (outs), (ins),
|
||||
"in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize16;
|
||||
"in{l}\t{%dx, %eax|eax, dx}", [], IIC_IN_RR>, OpSize32;
|
||||
|
||||
let Defs = [AL] in
|
||||
def IN8ri : Ii8<0xE4, RawFrm, (outs), (ins i8imm:$port),
|
||||
"in{b}\t{$port, %al|al, $port}", [], IIC_IN_RI>;
|
||||
let Defs = [AX] in
|
||||
def IN16ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
|
||||
"in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize;
|
||||
"in{w}\t{$port, %ax|ax, $port}", [], IIC_IN_RI>, OpSize16;
|
||||
let Defs = [EAX] in
|
||||
def IN32ri : Ii8<0xE5, RawFrm, (outs), (ins i8imm:$port),
|
||||
"in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize16;
|
||||
"in{l}\t{$port, %eax|eax, $port}", [], IIC_IN_RI>, OpSize32;
|
||||
|
||||
let Uses = [DX, AL] in
|
||||
def OUT8rr : I<0xEE, RawFrm, (outs), (ins),
|
||||
"out{b}\t{%al, %dx|dx, al}", [], IIC_OUT_RR>;
|
||||
let Uses = [DX, AX] in
|
||||
def OUT16rr : I<0xEF, RawFrm, (outs), (ins),
|
||||
"out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize;
|
||||
"out{w}\t{%ax, %dx|dx, ax}", [], IIC_OUT_RR>, OpSize16;
|
||||
let Uses = [DX, EAX] in
|
||||
def OUT32rr : I<0xEF, RawFrm, (outs), (ins),
|
||||
"out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize16;
|
||||
"out{l}\t{%eax, %dx|dx, eax}", [], IIC_OUT_RR>, OpSize32;
|
||||
|
||||
let Uses = [AL] in
|
||||
def OUT8ir : Ii8<0xE6, RawFrm, (outs), (ins i8imm:$port),
|
||||
"out{b}\t{%al, $port|$port, al}", [], IIC_OUT_IR>;
|
||||
let Uses = [AX] in
|
||||
def OUT16ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
|
||||
"out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize;
|
||||
"out{w}\t{%ax, $port|$port, ax}", [], IIC_OUT_IR>, OpSize16;
|
||||
let Uses = [EAX] in
|
||||
def OUT32ir : Ii8<0xE7, RawFrm, (outs), (ins i8imm:$port),
|
||||
"out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize16;
|
||||
"out{l}\t{%eax, $port|$port, eax}", [], IIC_OUT_IR>, OpSize32;
|
||||
|
||||
def IN8 : I<0x6C, RawFrmDst, (outs dstidx8:$dst), (ins),
|
||||
"insb\t{%dx, $dst|$dst, dx}", [], IIC_INS>;
|
||||
def IN16 : I<0x6D, RawFrmDst, (outs dstidx16:$dst), (ins),
|
||||
"insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize;
|
||||
"insw\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
|
||||
def IN32 : I<0x6D, RawFrmDst, (outs dstidx32:$dst), (ins),
|
||||
"ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize16;
|
||||
"ins{l|d}\t{%dx, $dst|$dst, dx}", [], IIC_INS>, OpSize32;
|
||||
} // SchedRW
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
@ -179,30 +179,30 @@ def GS_PREFIX : I<0x65, RawFrm, (outs), (ins), "gs", []>;
|
||||
|
||||
let SchedRW = [WriteMove] in {
|
||||
def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize;
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
|
||||
def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize16;
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>, OpSize32;
|
||||
def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
|
||||
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_REG_SR>;
|
||||
|
||||
def MOV16ms : I<0x8C, MRMDestMem, (outs i16mem:$dst), (ins SEGMENT_REG:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize;
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
|
||||
def MOV32ms : I<0x8C, MRMDestMem, (outs i32mem:$dst), (ins SEGMENT_REG:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize16;
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>, OpSize32;
|
||||
def MOV64ms : RI<0x8C, MRMDestMem, (outs i64mem:$dst), (ins SEGMENT_REG:$src),
|
||||
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_MEM_SR>;
|
||||
|
||||
def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize;
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
|
||||
def MOV32sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR32:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize16;
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>, OpSize32;
|
||||
def MOV64sr : RI<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR64:$src),
|
||||
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_REG>;
|
||||
|
||||
def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize;
|
||||
"mov{w}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
|
||||
def MOV32sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i32mem:$src),
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize16;
|
||||
"mov{l}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>, OpSize32;
|
||||
def MOV64sm : RI<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i64mem:$src),
|
||||
"mov{q}\t{$src, $dst|$dst, $src}", [], IIC_MOV_SR_MEM>;
|
||||
} // SchedRW
|
||||
@ -214,17 +214,19 @@ let SchedRW = [WriteSystem] in {
|
||||
def SWAPGS : I<0x01, MRM_F8, (outs), (ins), "swapgs", [], IIC_SWAPGS>, TB;
|
||||
|
||||
def LAR16rm : I<0x02, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB, OpSize;
|
||||
"lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
|
||||
OpSize16;
|
||||
def LAR16rr : I<0x02, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB, OpSize;
|
||||
"lar{w}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
|
||||
OpSize16;
|
||||
|
||||
// i16mem operand in LAR32rm and GR32 operand in LAR32rr is not a typo.
|
||||
def LAR32rm : I<0x02, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src),
|
||||
"lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def LAR32rr : I<0x02, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"lar{l}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
// i16mem operand in LAR64rm and GR32 operand in LAR32rr is not a typo.
|
||||
def LAR64rm : RI<0x02, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src),
|
||||
"lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RM>, TB;
|
||||
@ -232,15 +234,17 @@ def LAR64rr : RI<0x02, MRMSrcReg, (outs GR64:$dst), (ins GR32:$src),
|
||||
"lar{q}\t{$src, $dst|$dst, $src}", [], IIC_LAR_RR>, TB;
|
||||
|
||||
def LSL16rm : I<0x03, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src),
|
||||
"lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB, OpSize;
|
||||
"lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
|
||||
OpSize16;
|
||||
def LSL16rr : I<0x03, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src),
|
||||
"lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB, OpSize;
|
||||
"lsl{w}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
|
||||
OpSize16;
|
||||
def LSL32rm : I<0x03, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src),
|
||||
"lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def LSL32rr : I<0x03, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src),
|
||||
"lsl{l}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RR>, TB,
|
||||
OpSize16;
|
||||
OpSize32;
|
||||
def LSL64rm : RI<0x03, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src),
|
||||
"lsl{q}\t{$src, $dst|$dst, $src}", [], IIC_LSL_RM>, TB;
|
||||
def LSL64rr : RI<0x03, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
|
||||
@ -250,9 +254,9 @@ def INVLPG : I<0x01, MRM7m, (outs), (ins i8mem:$addr), "invlpg\t$addr",
|
||||
[], IIC_INVLPG>, TB;
|
||||
|
||||
def STR16r : I<0x00, MRM1r, (outs GR16:$dst), (ins),
|
||||
"str{w}\t$dst", [], IIC_STR>, TB, OpSize;
|
||||
"str{w}\t$dst", [], IIC_STR>, TB, OpSize16;
|
||||
def STR32r : I<0x00, MRM1r, (outs GR32:$dst), (ins),
|
||||
"str{l}\t$dst", [], IIC_STR>, TB, OpSize16;
|
||||
"str{l}\t$dst", [], IIC_STR>, TB, OpSize32;
|
||||
def STR64r : RI<0x00, MRM1r, (outs GR64:$dst), (ins),
|
||||
"str{q}\t$dst", [], IIC_STR>, TB;
|
||||
def STRm : I<0x00, MRM1m, (outs i16mem:$dst), (ins),
|
||||
@ -265,38 +269,38 @@ def LTRm : I<0x00, MRM3m, (outs), (ins i16mem:$src),
|
||||
|
||||
def PUSHCS16 : I<0x0E, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%cs|cs}", [], IIC_PUSH_SR>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def PUSHCS32 : I<0x0E, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%cs|cs}", [], IIC_PUSH_CS>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def PUSHSS16 : I<0x16, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%ss|ss}", [], IIC_PUSH_SR>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def PUSHSS32 : I<0x16, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%ss|ss}", [], IIC_PUSH_SR>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def PUSHDS16 : I<0x1E, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%ds|ds}", [], IIC_PUSH_SR>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def PUSHDS32 : I<0x1E, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%ds|ds}", [], IIC_PUSH_SR>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def PUSHES16 : I<0x06, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%es|es}", [], IIC_PUSH_SR>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def PUSHES32 : I<0x06, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%es|es}", [], IIC_PUSH_SR>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def PUSHFS16 : I<0xa0, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize, TB;
|
||||
"push{w}\t{%fs|fs}", [], IIC_PUSH_SR>, OpSize16, TB;
|
||||
def PUSHFS32 : I<0xa0, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%fs|fs}", [], IIC_PUSH_SR>, TB,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def PUSHGS16 : I<0xa8, RawFrm, (outs), (ins),
|
||||
"push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize, TB;
|
||||
"push{w}\t{%gs|gs}", [], IIC_PUSH_SR>, OpSize16, TB;
|
||||
def PUSHGS32 : I<0xa8, RawFrm, (outs), (ins),
|
||||
"push{l}\t{%gs|gs}", [], IIC_PUSH_SR>, TB,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def PUSHFS64 : I<0xa0, RawFrm, (outs), (ins),
|
||||
"push{q}\t{%fs|fs}", [], IIC_PUSH_SR>, TB, Requires<[In64BitMode]>;
|
||||
def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
|
||||
@ -305,70 +309,70 @@ def PUSHGS64 : I<0xa8, RawFrm, (outs), (ins),
|
||||
// No "pop cs" instruction.
|
||||
def POPSS16 : I<0x17, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%ss|ss}", [], IIC_POP_SR_SS>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def POPSS32 : I<0x17, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%ss|ss}", [], IIC_POP_SR_SS>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
|
||||
def POPDS16 : I<0x1F, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%ds|ds}", [], IIC_POP_SR>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def POPDS32 : I<0x1F, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%ds|ds}", [], IIC_POP_SR>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
|
||||
def POPES16 : I<0x07, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%es|es}", [], IIC_POP_SR>,
|
||||
OpSize, Requires<[Not64BitMode]>;
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
def POPES32 : I<0x07, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%es|es}", [], IIC_POP_SR>,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
|
||||
def POPFS16 : I<0xa1, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize, TB;
|
||||
"pop{w}\t{%fs|fs}", [], IIC_POP_SR>, OpSize16, TB;
|
||||
def POPFS32 : I<0xa1, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%fs|fs}", [], IIC_POP_SR>, TB,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def POPFS64 : I<0xa1, RawFrm, (outs), (ins),
|
||||
"pop{q}\t{%fs|fs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
|
||||
|
||||
def POPGS16 : I<0xa9, RawFrm, (outs), (ins),
|
||||
"pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize, TB;
|
||||
"pop{w}\t{%gs|gs}", [], IIC_POP_SR>, OpSize16, TB;
|
||||
def POPGS32 : I<0xa9, RawFrm, (outs), (ins),
|
||||
"pop{l}\t{%gs|gs}", [], IIC_POP_SR>, TB,
|
||||
OpSize16, Requires<[Not64BitMode]>;
|
||||
OpSize32, Requires<[Not64BitMode]>;
|
||||
def POPGS64 : I<0xa9, RawFrm, (outs), (ins),
|
||||
"pop{q}\t{%gs|gs}", [], IIC_POP_SR>, TB, Requires<[In64BitMode]>;
|
||||
|
||||
|
||||
def LDS16rm : I<0xc5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
|
||||
"lds{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
|
||||
def LDS32rm : I<0xc5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
|
||||
"lds{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
|
||||
|
||||
def LSS16rm : I<0xb2, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
|
||||
"lss{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
|
||||
def LSS32rm : I<0xb2, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
|
||||
"lss{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
|
||||
def LSS64rm : RI<0xb2, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
||||
"lss{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
|
||||
|
||||
def LES16rm : I<0xc4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize;
|
||||
"les{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
|
||||
def LES32rm : I<0xc4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize16;
|
||||
"les{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, OpSize32;
|
||||
|
||||
def LFS16rm : I<0xb4, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
|
||||
"lfs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
|
||||
def LFS32rm : I<0xb4, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
|
||||
"lfs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
|
||||
def LFS64rm : RI<0xb4, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
||||
"lfs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
|
||||
|
||||
def LGS16rm : I<0xb5, MRMSrcMem, (outs GR16:$dst), (ins opaque32mem:$src),
|
||||
"lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize;
|
||||
"lgs{w}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
|
||||
def LGS32rm : I<0xb5, MRMSrcMem, (outs GR32:$dst), (ins opaque48mem:$src),
|
||||
"lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize16;
|
||||
"lgs{l}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB, OpSize32;
|
||||
|
||||
def LGS64rm : RI<0xb5, MRMSrcMem, (outs GR64:$dst), (ins opaque80mem:$src),
|
||||
"lgs{q}\t{$src, $dst|$dst, $src}", [], IIC_LXS>, TB;
|
||||
@ -389,23 +393,23 @@ def VERWm : I<0x00, MRM5m, (outs), (ins i16mem:$seg),
|
||||
|
||||
let SchedRW = [WriteSystem] in {
|
||||
def SGDT16m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
|
||||
"sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize, Requires<[Not64BitMode]>;
|
||||
"sgdt{w}\t$dst", [], IIC_SGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
|
||||
def SGDT32m : I<0x01, MRM0m, (outs opaque48mem:$dst), (ins),
|
||||
"sgdt{l}\t$dst", [], IIC_SGDT>, OpSize16, TB, Requires <[Not64BitMode]>;
|
||||
"sgdt{l}\t$dst", [], IIC_SGDT>, OpSize32, TB, Requires <[Not64BitMode]>;
|
||||
def SGDT64m : I<0x01, MRM0m, (outs opaque80mem:$dst), (ins),
|
||||
"sgdt{q}\t$dst", [], IIC_SGDT>, TB, Requires <[In64BitMode]>;
|
||||
def SIDT16m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
|
||||
"sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize, Requires<[Not64BitMode]>;
|
||||
"sidt{w}\t$dst", [], IIC_SIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
|
||||
def SIDT32m : I<0x01, MRM1m, (outs opaque48mem:$dst), (ins),
|
||||
"sidt{l}\t$dst", []>, OpSize16, TB, Requires <[Not64BitMode]>;
|
||||
"sidt{l}\t$dst", []>, OpSize32, TB, Requires <[Not64BitMode]>;
|
||||
def SIDT64m : I<0x01, MRM1m, (outs opaque80mem:$dst), (ins),
|
||||
"sidt{q}\t$dst", []>, TB, Requires <[In64BitMode]>;
|
||||
def SLDT16r : I<0x00, MRM0r, (outs GR16:$dst), (ins),
|
||||
"sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize;
|
||||
"sldt{w}\t$dst", [], IIC_SLDT>, TB, OpSize16;
|
||||
def SLDT16m : I<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
||||
"sldt{w}\t$dst", [], IIC_SLDT>, TB;
|
||||
def SLDT32r : I<0x00, MRM0r, (outs GR32:$dst), (ins),
|
||||
"sldt{l}\t$dst", [], IIC_SLDT>, OpSize16, TB;
|
||||
"sldt{l}\t$dst", [], IIC_SLDT>, OpSize32, TB;
|
||||
|
||||
// LLDT is not interpreted specially in 64-bit mode because there is no sign
|
||||
// extension.
|
||||
@ -415,15 +419,15 @@ def SLDT64m : RI<0x00, MRM0m, (outs i16mem:$dst), (ins),
|
||||
"sldt{q}\t$dst", [], IIC_SLDT>, TB;
|
||||
|
||||
def LGDT16m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
|
||||
"lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize, Requires<[Not64BitMode]>;
|
||||
"lgdt{w}\t$src", [], IIC_LGDT>, TB, OpSize16, Requires<[Not64BitMode]>;
|
||||
def LGDT32m : I<0x01, MRM2m, (outs), (ins opaque48mem:$src),
|
||||
"lgdt{l}\t$src", [], IIC_LGDT>, OpSize16, TB, Requires<[Not64BitMode]>;
|
||||
"lgdt{l}\t$src", [], IIC_LGDT>, OpSize32, TB, Requires<[Not64BitMode]>;
|
||||
def LGDT64m : I<0x01, MRM2m, (outs), (ins opaque80mem:$src),
|
||||
"lgdt{q}\t$src", [], IIC_LGDT>, TB, Requires<[In64BitMode]>;
|
||||
def LIDT16m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
|
||||
"lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize, Requires<[Not64BitMode]>;
|
||||
"lidt{w}\t$src", [], IIC_LIDT>, TB, OpSize16, Requires<[Not64BitMode]>;
|
||||
def LIDT32m : I<0x01, MRM3m, (outs), (ins opaque48mem:$src),
|
||||
"lidt{l}\t$src", [], IIC_LIDT>, OpSize16, TB, Requires<[Not64BitMode]>;
|
||||
"lidt{l}\t$src", [], IIC_LIDT>, OpSize32, TB, Requires<[Not64BitMode]>;
|
||||
def LIDT64m : I<0x01, MRM3m, (outs), (ins opaque80mem:$src),
|
||||
"lidt{q}\t$src", [], IIC_LIDT>, TB, Requires<[In64BitMode]>;
|
||||
def LLDT16r : I<0x00, MRM2r, (outs), (ins GR16:$src),
|
||||
@ -440,9 +444,9 @@ def RDMSR : I<0x32, RawFrm, (outs), (ins), "rdmsr", [], IIC_RDMSR>, TB;
|
||||
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", [], IIC_RDPMC>, TB;
|
||||
|
||||
def SMSW16r : I<0x01, MRM4r, (outs GR16:$dst), (ins),
|
||||
"smsw{w}\t$dst", [], IIC_SMSW>, OpSize, TB;
|
||||
"smsw{w}\t$dst", [], IIC_SMSW>, OpSize16, TB;
|
||||
def SMSW32r : I<0x01, MRM4r, (outs GR32:$dst), (ins),
|
||||
"smsw{l}\t$dst", [], IIC_SMSW>, OpSize16, TB;
|
||||
"smsw{l}\t$dst", [], IIC_SMSW>, OpSize32, TB;
|
||||
// no m form encodable; use SMSW16m
|
||||
def SMSW64r : RI<0x01, MRM4r, (outs GR64:$dst), (ins),
|
||||
"smsw{q}\t$dst", [], IIC_SMSW>, TB;
|
||||
|
||||
@ -89,6 +89,10 @@ namespace X86Local {
|
||||
enum {
|
||||
VEX = 1, XOP = 2, EVEX = 3
|
||||
};
|
||||
|
||||
enum {
|
||||
OpSize16 = 1, OpSize32 = 2
|
||||
};
|
||||
}
|
||||
|
||||
// If rows are added to the opcode extension tables, then corresponding entries
|
||||
@ -234,8 +238,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
|
||||
Form = byteFromRec(Rec, "FormBits");
|
||||
Encoding = byteFromRec(Rec->getValueAsDef("OpEnc"), "Value");
|
||||
|
||||
HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
|
||||
HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
|
||||
OpSize = byteFromRec(Rec->getValueAsDef("OpSize"), "Value");
|
||||
HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
|
||||
HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
|
||||
HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
|
||||
@ -406,13 +409,13 @@ InstructionContext RecognizableInstr::insnContext() const {
|
||||
else
|
||||
insnContext = IC_VEX;
|
||||
} else if (Is64Bit || HasREX_WPrefix) {
|
||||
if (HasREX_WPrefix && (HasOpSizePrefix || OpPrefix == X86Local::PD))
|
||||
if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
|
||||
insnContext = IC_64BIT_REXW_OPSIZE;
|
||||
else if (HasOpSizePrefix && OpPrefix == X86Local::XD)
|
||||
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
|
||||
insnContext = IC_64BIT_XD_OPSIZE;
|
||||
else if (HasOpSizePrefix && OpPrefix == X86Local::XS)
|
||||
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
|
||||
insnContext = IC_64BIT_XS_OPSIZE;
|
||||
else if (HasOpSizePrefix || OpPrefix == X86Local::PD)
|
||||
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
|
||||
insnContext = IC_64BIT_OPSIZE;
|
||||
else if (HasAdSizePrefix)
|
||||
insnContext = IC_64BIT_ADSIZE;
|
||||
@ -429,11 +432,11 @@ InstructionContext RecognizableInstr::insnContext() const {
|
||||
else
|
||||
insnContext = IC_64BIT;
|
||||
} else {
|
||||
if (HasOpSizePrefix && OpPrefix == X86Local::XD)
|
||||
if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
|
||||
insnContext = IC_XD_OPSIZE;
|
||||
else if (HasOpSizePrefix && OpPrefix == X86Local::XS)
|
||||
else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
|
||||
insnContext = IC_XS_OPSIZE;
|
||||
else if (HasOpSizePrefix || OpPrefix == X86Local::PD)
|
||||
else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
|
||||
insnContext = IC_OPSIZE;
|
||||
else if (HasAdSizePrefix)
|
||||
insnContext = IC_ADSIZE;
|
||||
@ -495,7 +498,7 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
|
||||
const unsigned *operandMapping,
|
||||
OperandEncoding (*encodingFromString)
|
||||
(const std::string&,
|
||||
bool hasOpSizePrefix)) {
|
||||
uint8_t OpSize)) {
|
||||
if (optional) {
|
||||
if (physicalOperandIndex >= numPhysicalOperands)
|
||||
return;
|
||||
@ -513,11 +516,9 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
|
||||
const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
|
||||
|
||||
Spec->operands[operandIndex].encoding = encodingFromString(typeName,
|
||||
HasOpSizePrefix);
|
||||
OpSize);
|
||||
Spec->operands[operandIndex].type = typeFromString(typeName,
|
||||
HasREX_WPrefix,
|
||||
HasOpSizePrefix,
|
||||
HasOpSize16Prefix);
|
||||
HasREX_WPrefix, OpSize);
|
||||
|
||||
++operandIndex;
|
||||
++physicalOperandIndex;
|
||||
@ -1151,21 +1152,19 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
|
||||
#define TYPE(str, type) if (s == str) return type;
|
||||
OperandType RecognizableInstr::typeFromString(const std::string &s,
|
||||
bool hasREX_WPrefix,
|
||||
bool hasOpSizePrefix,
|
||||
bool hasOpSize16Prefix) {
|
||||
uint8_t OpSize) {
|
||||
if(hasREX_WPrefix) {
|
||||
// For instructions with a REX_W prefix, a declared 32-bit register encoding
|
||||
// is special.
|
||||
TYPE("GR32", TYPE_R32)
|
||||
}
|
||||
if(hasOpSizePrefix) {
|
||||
// For instructions with an OpSize prefix, a declared 16-bit register or
|
||||
if(OpSize == X86Local::OpSize16) {
|
||||
// For OpSize16 instructions, a declared 16-bit register or
|
||||
// immediate encoding is special.
|
||||
TYPE("GR16", TYPE_Rv)
|
||||
TYPE("i16imm", TYPE_IMMv)
|
||||
}
|
||||
if(hasOpSize16Prefix) {
|
||||
// For instructions with an OpSize16 prefix, a declared 32-bit register or
|
||||
} else if(OpSize == X86Local::OpSize32) {
|
||||
// For OpSize32 instructions, a declared 32-bit register or
|
||||
// immediate encoding is special.
|
||||
TYPE("GR32", TYPE_Rv)
|
||||
}
|
||||
@ -1262,10 +1261,10 @@ OperandType RecognizableInstr::typeFromString(const std::string &s,
|
||||
#undef TYPE
|
||||
|
||||
#define ENCODING(str, encoding) if (s == str) return encoding;
|
||||
OperandEncoding RecognizableInstr::immediateEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
if(!hasOpSizePrefix) {
|
||||
OperandEncoding
|
||||
RecognizableInstr::immediateEncodingFromString(const std::string &s,
|
||||
uint8_t OpSize) {
|
||||
if(OpSize != X86Local::OpSize16) {
|
||||
// For instructions without an OpSize prefix, a declared 16-bit register or
|
||||
// immediate encoding is special.
|
||||
ENCODING("i16imm", ENCODING_IW)
|
||||
@ -1296,9 +1295,9 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString
|
||||
llvm_unreachable("Unhandled immediate encoding");
|
||||
}
|
||||
|
||||
OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
OperandEncoding
|
||||
RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
|
||||
uint8_t OpSize) {
|
||||
ENCODING("RST", ENCODING_FP)
|
||||
ENCODING("GR16", ENCODING_RM)
|
||||
ENCODING("GR32", ENCODING_RM)
|
||||
@ -1322,9 +1321,9 @@ OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
|
||||
llvm_unreachable("Unhandled R/M register encoding");
|
||||
}
|
||||
|
||||
OperandEncoding RecognizableInstr::roRegisterEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
OperandEncoding
|
||||
RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
|
||||
uint8_t OpSize) {
|
||||
ENCODING("GR16", ENCODING_REG)
|
||||
ENCODING("GR32", ENCODING_REG)
|
||||
ENCODING("GR32orGR64", ENCODING_REG)
|
||||
@ -1353,9 +1352,9 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString
|
||||
llvm_unreachable("Unhandled reg/opcode register encoding");
|
||||
}
|
||||
|
||||
OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
OperandEncoding
|
||||
RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
|
||||
uint8_t OpSize) {
|
||||
ENCODING("GR32", ENCODING_VVVV)
|
||||
ENCODING("GR64", ENCODING_VVVV)
|
||||
ENCODING("FR32", ENCODING_VVVV)
|
||||
@ -1374,9 +1373,9 @@ OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
|
||||
llvm_unreachable("Unhandled VEX.vvvv register encoding");
|
||||
}
|
||||
|
||||
OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
OperandEncoding
|
||||
RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
|
||||
uint8_t OpSize) {
|
||||
ENCODING("VK1WM", ENCODING_WRITEMASK)
|
||||
ENCODING("VK8WM", ENCODING_WRITEMASK)
|
||||
ENCODING("VK16WM", ENCODING_WRITEMASK)
|
||||
@ -1384,9 +1383,9 @@ OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
|
||||
llvm_unreachable("Unhandled mask register encoding");
|
||||
}
|
||||
|
||||
OperandEncoding RecognizableInstr::memoryEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
OperandEncoding
|
||||
RecognizableInstr::memoryEncodingFromString(const std::string &s,
|
||||
uint8_t OpSize) {
|
||||
ENCODING("i16mem", ENCODING_RM)
|
||||
ENCODING("i32mem", ENCODING_RM)
|
||||
ENCODING("i64mem", ENCODING_RM)
|
||||
@ -1420,10 +1419,10 @@ OperandEncoding RecognizableInstr::memoryEncodingFromString
|
||||
llvm_unreachable("Unhandled memory encoding");
|
||||
}
|
||||
|
||||
OperandEncoding RecognizableInstr::relocationEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
if(!hasOpSizePrefix) {
|
||||
OperandEncoding
|
||||
RecognizableInstr::relocationEncodingFromString(const std::string &s,
|
||||
uint8_t OpSize) {
|
||||
if(OpSize != X86Local::OpSize16) {
|
||||
// For instructions without an OpSize prefix, a declared 16-bit register or
|
||||
// immediate encoding is special.
|
||||
ENCODING("i16imm", ENCODING_IW)
|
||||
@ -1457,9 +1456,9 @@ OperandEncoding RecognizableInstr::relocationEncodingFromString
|
||||
llvm_unreachable("Unhandled relocation encoding");
|
||||
}
|
||||
|
||||
OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
|
||||
(const std::string &s,
|
||||
bool hasOpSizePrefix) {
|
||||
OperandEncoding
|
||||
RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
|
||||
uint8_t OpSize) {
|
||||
ENCODING("GR32", ENCODING_Rv)
|
||||
ENCODING("GR64", ENCODING_RO)
|
||||
ENCODING("GR16", ENCODING_Rv)
|
||||
|
||||
@ -48,10 +48,8 @@ private:
|
||||
uint8_t Form;
|
||||
// The encoding field from the record
|
||||
uint8_t Encoding;
|
||||
/// The hasOpSizePrefix field from the record
|
||||
bool HasOpSizePrefix;
|
||||
/// The hasOpSize16Prefix field from the record
|
||||
bool HasOpSize16Prefix;
|
||||
/// The OpSize field from the record
|
||||
uint8_t OpSize;
|
||||
/// The hasAdSizePrefix field from the record
|
||||
bool HasAdSizePrefix;
|
||||
/// The hasREX_WPrefix field from the record
|
||||
@ -147,47 +145,44 @@ private:
|
||||
/// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W
|
||||
/// prefix. If it does, 32-bit register operands stay
|
||||
/// 32-bit regardless of the operand size.
|
||||
/// @param hasOpSizePrefix Indicates whether the instruction has an OpSize
|
||||
/// prefix. If it does not, then 16-bit register
|
||||
/// operands stay 16-bit.
|
||||
/// @param OpSize Indicates the operand size of the instruction.
|
||||
/// If register size does not match OpSize, then
|
||||
/// register sizes keep their size.
|
||||
/// @return - The operand's type.
|
||||
static OperandType typeFromString(const std::string& s,
|
||||
bool isSSE,
|
||||
bool hasREX_WPrefix,
|
||||
bool hasOpSizePrefix);
|
||||
|
||||
static OperandType typeFromString(const std::string& s,
|
||||
bool hasREX_WPrefix, uint8_t OpSize);
|
||||
|
||||
/// immediateEncodingFromString - Translates an immediate encoding from the
|
||||
/// string provided in the LLVM tables to an OperandEncoding for use in
|
||||
/// the operand specifier.
|
||||
///
|
||||
/// @param s - See typeFromString().
|
||||
/// @param hasOpSizePrefix - Indicates whether the instruction has an OpSize
|
||||
/// prefix. If it does not, then 16-bit immediate
|
||||
/// operands stay 16-bit.
|
||||
/// @return - The operand's encoding.
|
||||
/// @param s - See typeFromString().
|
||||
/// @param OpSize - Indicates whether this is an OpSize16 instruction.
|
||||
/// If it is not, then 16-bit immediate operands stay 16-bit.
|
||||
/// @return - The operand's encoding.
|
||||
static OperandEncoding immediateEncodingFromString(const std::string &s,
|
||||
bool hasOpSizePrefix);
|
||||
|
||||
uint8_t OpSize);
|
||||
|
||||
/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
|
||||
/// handles operands that are in the REG field of the ModR/M byte.
|
||||
static OperandEncoding rmRegisterEncodingFromString(const std::string &s,
|
||||
bool hasOpSizePrefix);
|
||||
|
||||
uint8_t OpSize);
|
||||
|
||||
/// rmRegisterEncodingFromString - Like immediateEncodingFromString, but
|
||||
/// handles operands that are in the REG field of the ModR/M byte.
|
||||
static OperandEncoding roRegisterEncodingFromString(const std::string &s,
|
||||
bool hasOpSizePrefix);
|
||||
uint8_t OpSize);
|
||||
static OperandEncoding memoryEncodingFromString(const std::string &s,
|
||||
bool hasOpSizePrefix);
|
||||
uint8_t OpSize);
|
||||
static OperandEncoding relocationEncodingFromString(const std::string &s,
|
||||
bool hasOpSizePrefix);
|
||||
uint8_t OpSize);
|
||||
static OperandEncoding opcodeModifierEncodingFromString(const std::string &s,
|
||||
bool hasOpSizePrefix);
|
||||
uint8_t OpSize);
|
||||
static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s,
|
||||
bool HasOpSizePrefix);
|
||||
uint8_t OpSize);
|
||||
static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s,
|
||||
bool HasOpSizePrefix);
|
||||
|
||||
uint8_t OpSize);
|
||||
|
||||
/// handleOperand - Converts a single operand from the LLVM table format to
|
||||
/// the emitted table format, handling any duplicate operands it encounters
|
||||
/// and then one non-duplicate.
|
||||
@ -213,8 +208,8 @@ private:
|
||||
const unsigned *operandMapping,
|
||||
OperandEncoding (*encodingFromString)
|
||||
(const std::string&,
|
||||
bool hasOpSizePrefix));
|
||||
|
||||
uint8_t OpSize));
|
||||
|
||||
/// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter()
|
||||
/// filters out many instructions, at various points in decoding we
|
||||
/// determine that the instruction should not actually be decodable. In
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user