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[C++11] Add 'override' keywords and remove 'virtual'. Additionally add 'final' and leave 'virtual' on some methods that are marked virtual without overriding anything and have no obvious overrides themselves. NVPTX edition

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207505 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2014-04-29 07:57:44 +00:00
parent e651935ab8
commit 6b7b725179
19 changed files with 112 additions and 108 deletions
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4
lib/Target/NVPTX/InstPrinter/NVPTXInstPrinter.h
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@ -27,8 +27,8 @@ public:
NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
void printRegName(raw_ostream &OS, unsigned RegNo) const override;
void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override;
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, raw_ostream &O);

6
lib/Target/NVPTX/NVPTXAllocaHoisting.h
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@ -30,17 +30,17 @@ public:
static char ID; // Pass ID
NVPTXAllocaHoisting() : FunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<DataLayoutPass>();
AU.addPreserved("stack-protector");
AU.addPreserved<MachineFunctionAnalysis>();
}
virtual const char *getPassName() const {
const char *getPassName() const override {
return "NVPTX specific alloca hoisting";
}
virtual bool runOnFunction(Function &function);
bool runOnFunction(Function &function) override;
};
extern FunctionPass *createAllocaHoisting();

22
lib/Target/NVPTX/NVPTXAsmPrinter.h
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@ -189,20 +189,20 @@ class LLVM_LIBRARY_VISIBILITY NVPTXAsmPrinter : public AsmPrinter {
friend class AggBuffer;
virtual void emitSrcInText(StringRef filename, unsigned line);
void emitSrcInText(StringRef filename, unsigned line);
private:
virtual const char *getPassName() const { return "NVPTX Assembly Printer"; }
const char *getPassName() const override { return "NVPTX Assembly Printer"; }
const Function *F;
std::string CurrentFnName;
void EmitFunctionEntryLabel();
void EmitFunctionBodyStart();
void EmitFunctionBodyEnd();
void emitImplicitDef(const MachineInstr *MI) const;
void EmitFunctionEntryLabel() override;
void EmitFunctionBodyStart() override;
void EmitFunctionBodyEnd() override;
void emitImplicitDef(const MachineInstr *MI) const override;
void EmitInstruction(const MachineInstr *);
void EmitInstruction(const MachineInstr *) override;
void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI);
bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp);
MCOperand GetSymbolRef(const MCSymbol *Symbol);
@ -234,15 +234,15 @@ private:
void printReturnValStr(const MachineFunction &MF, raw_ostream &O);
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &);
raw_ostream &) override;
void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O,
const char *Modifier = nullptr);
bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
unsigned AsmVariant, const char *ExtraCode,
raw_ostream &);
raw_ostream &) override;
protected:
bool doInitialization(Module &M);
bool doFinalization(Module &M);
bool doInitialization(Module &M) override;
bool doFinalization(Module &M) override;
private:
std::string CurrentBankselLabelInBasicBlock;

2
lib/Target/NVPTX/NVPTXAssignValidGlobalNames.cpp
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@ -33,7 +33,7 @@ public:
static char ID;
NVPTXAssignValidGlobalNames() : ModulePass(ID) {}
virtual bool runOnModule(Module &M);
bool runOnModule(Module &M) override;
/// \brief Clean up the name to remove symbols invalid in PTX.
std::string cleanUpName(StringRef Name);

10
lib/Target/NVPTX/NVPTXFrameLowering.h
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@ -28,13 +28,13 @@ public:
: TargetFrameLowering(TargetFrameLowering::StackGrowsUp, 8, 0), tm(_tm),
is64bit(_is64bit) {}
virtual bool hasFP(const MachineFunction &MF) const;
virtual void emitPrologue(MachineFunction &MF) const;
virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
bool hasFP(const MachineFunction &MF) const override;
void emitPrologue(MachineFunction &MF) const override;
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const override;
};
} // End llvm namespace

5
lib/Target/NVPTX/NVPTXGenericToNVVM.cpp
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@ -40,10 +40,9 @@ public:
GenericToNVVM() : ModulePass(ID) {}
virtual bool runOnModule(Module &M);
bool runOnModule(Module &M) override;
virtual void getAnalysisUsage(AnalysisUsage &AU) const {
}
void getAnalysisUsage(AnalysisUsage &AU) const override {}
private:
Value *getOrInsertCVTA(Module *M, Function *F, GlobalVariable *GV,

9
lib/Target/NVPTX/NVPTXISelDAGToDAG.h
View File

@ -44,19 +44,20 @@ public:
CodeGenOpt::Level OptLevel);
// Pass Name
virtual const char *getPassName() const {
const char *getPassName() const override {
return "NVPTX DAG->DAG Pattern Instruction Selection";
}
const NVPTXSubtarget &Subtarget;
virtual bool SelectInlineAsmMemoryOperand(
const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps);
bool SelectInlineAsmMemoryOperand(const SDValue &Op,
char ConstraintCode,
std::vector<SDValue> &OutOps) override;
private:
// Include the pieces autogenerated from the target description.
#include "NVPTXGenDAGISel.inc"
SDNode *Select(SDNode *N);
SDNode *Select(SDNode *N) override;
SDNode *SelectIntrinsicNoChain(SDNode *N);
SDNode *SelectTexSurfHandle(SDNode *N);
SDNode *SelectLoad(SDNode *N);

44
lib/Target/NVPTX/NVPTXISelLowering.h
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@ -173,68 +173,70 @@ enum NodeType {
class NVPTXTargetLowering : public TargetLowering {
public:
explicit NVPTXTargetLowering(NVPTXTargetMachine &TM);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerGlobalAddress(const GlobalValue *GV, int64_t Offset,
SelectionDAG &DAG) const;
virtual const char *getTargetNodeName(unsigned Opcode) const;
const char *getTargetNodeName(unsigned Opcode) const override;
bool isTypeSupportedInIntrinsic(MVT VT) const;
bool getTgtMemIntrinsic(IntrinsicInfo &Info, const CallInst &I,
unsigned Intrinsic) const;
unsigned Intrinsic) const override;
/// isLegalAddressingMode - Return true if the addressing mode represented
/// by AM is legal for this target, for a load/store of the specified type
/// Used to guide target specific optimizations, like loop strength
/// reduction (LoopStrengthReduce.cpp) and memory optimization for
/// address mode (CodeGenPrepare.cpp)
virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const;
bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
/// getFunctionAlignment - Return the Log2 alignment of this function.
virtual unsigned getFunctionAlignment(const Function *F) const;
unsigned getFunctionAlignment(const Function *F) const;
virtual EVT getSetCCResultType(LLVMContext &, EVT VT) const {
EVT getSetCCResultType(LLVMContext &, EVT VT) const override {
if (VT.isVector())
return MVT::getVectorVT(MVT::i1, VT.getVectorNumElements());
return MVT::i1;
}
ConstraintType getConstraintType(const std::string &Constraint) const;
ConstraintType
getConstraintType(const std::string &Constraint) const override;
std::pair<unsigned, const TargetRegisterClass *>
getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const;
getRegForInlineAsmConstraint(const std::string &Constraint,
MVT VT) const override;
virtual SDValue LowerFormalArguments(
SDValue LowerFormalArguments(
SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
SmallVectorImpl<SDValue> &InVals) const;
SmallVectorImpl<SDValue> &InVals) const override;
virtual SDValue
LowerCall(CallLoweringInfo &CLI, SmallVectorImpl<SDValue> &InVals) const;
SDValue LowerCall(CallLoweringInfo &CLI,
SmallVectorImpl<SDValue> &InVals) const override;
std::string getPrototype(Type *, const ArgListTy &,
const SmallVectorImpl<ISD::OutputArg> &,
unsigned retAlignment,
const ImmutableCallSite *CS) const;
virtual SDValue
SDValue
LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
const SmallVectorImpl<ISD::OutputArg> &Outs,
const SmallVectorImpl<SDValue> &OutVals, SDLoc dl,
SelectionDAG &DAG) const;
SelectionDAG &DAG) const override;
virtual void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const;
void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
std::vector<SDValue> &Ops,
SelectionDAG &DAG) const override;
NVPTXTargetMachine *nvTM;
// PTX always uses 32-bit shift amounts
virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
virtual bool shouldSplitVectorType(EVT VT) const override;
bool shouldSplitVectorType(EVT VT) const override;
private:
const NVPTXSubtarget &nvptxSubtarget; // cache the subtarget here
@ -253,8 +255,8 @@ private:
SDValue LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const;
virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const;
void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
SelectionDAG &DAG) const override;
unsigned getArgumentAlignment(SDValue Callee, const ImmutableCallSite *CS,
Type *Ty, unsigned Idx) const;

2
lib/Target/NVPTX/NVPTXImageOptimizer.cpp
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@ -33,7 +33,7 @@ private:
public:
NVPTXImageOptimizer();
bool runOnFunction(Function &F);
bool runOnFunction(Function &F) override;
private:
bool replaceIsTypePSampler(Instruction &I);

16
lib/Target/NVPTX/NVPTXInstrInfo.h
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@ -30,7 +30,7 @@ class NVPTXInstrInfo : public NVPTXGenInstrInfo {
public:
explicit NVPTXInstrInfo(NVPTXTargetMachine &TM);
virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; }
/* The following virtual functions are used in register allocation.
* They are not implemented because the existing interface and the logic
@ -50,9 +50,9 @@ public:
* const TargetRegisterClass *RC) const;
*/
virtual void copyPhysReg(
void copyPhysReg(
MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
unsigned DestReg, unsigned SrcReg, bool KillSrc) const;
unsigned DestReg, unsigned SrcReg, bool KillSrc) const override;
virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
unsigned &DestReg) const;
bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const;
@ -61,13 +61,13 @@ public:
virtual bool CanTailMerge(const MachineInstr *MI) const;
// Branch analysis.
virtual bool AnalyzeBranch(
bool AnalyzeBranch(
MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
virtual unsigned InsertBranch(
SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const override;
unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
unsigned InsertBranch(
MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const override;
unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const {
return MI.getOperand(2).getImm();
}

6
lib/Target/NVPTX/NVPTXLowerAggrCopies.h
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@ -27,17 +27,17 @@ struct NVPTXLowerAggrCopies : public FunctionPass {
NVPTXLowerAggrCopies() : FunctionPass(ID) {}
void getAnalysisUsage(AnalysisUsage &AU) const {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<DataLayoutPass>();
AU.addPreserved("stack-protector");
AU.addPreserved<MachineFunctionAnalysis>();
}
virtual bool runOnFunction(Function &F);
bool runOnFunction(Function &F) override;
static const unsigned MaxAggrCopySize = 128;
virtual const char *getPassName() const {
const char *getPassName() const override {
return "Lower aggregate copies/intrinsics into loops";
}
};

10
lib/Target/NVPTX/NVPTXMCExpr.h
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@ -61,18 +61,18 @@ public:
/// @}
void PrintImpl(raw_ostream &OS) const;
void PrintImpl(raw_ostream &OS) const override;
bool EvaluateAsRelocatableImpl(MCValue &Res,
const MCAsmLayout *Layout) const {
const MCAsmLayout *Layout) const override {
return false;
}
void AddValueSymbols(MCAssembler *) const {};
const MCSection *FindAssociatedSection() const {
void AddValueSymbols(MCAssembler *) const override {};
const MCSection *FindAssociatedSection() const override {
return nullptr;
}
// There are no TLS NVPTXMCExprs at the moment.
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const {}
void fixELFSymbolsInTLSFixups(MCAssembler &Asm) const override {}
static bool classof(const MCExpr *E) {
return E->getKind() == MCExpr::Target;

2
lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp
View File

@ -33,7 +33,7 @@ public:
static char ID;
NVPTXPrologEpilogPass() : MachineFunctionPass(ID) {}
virtual bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
private:
void calculateFrameObjectOffsets(MachineFunction &Fn);

20
lib/Target/NVPTX/NVPTXRegisterInfo.h
View File

@ -41,22 +41,22 @@ public:
//------------------------------------------------------
// NVPTX callee saved registers
virtual const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const;
const MCPhysReg *
getCalleeSavedRegs(const MachineFunction *MF = nullptr) const override;
// NVPTX callee saved register classes
virtual const TargetRegisterClass *const *
getCalleeSavedRegClasses(const MachineFunction *MF) const;
getCalleeSavedRegClasses(const MachineFunction *MF) const final;
virtual BitVector getReservedRegs(const MachineFunction &MF) const;
BitVector getReservedRegs(const MachineFunction &MF) const override;
virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const;
void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const;
virtual unsigned getFrameRegister(const MachineFunction &MF) const;
virtual unsigned getRARegister() const;
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const final;
unsigned getFrameRegister(const MachineFunction &MF) const override;
virtual unsigned getRARegister() const final;
ManagedStringPool *getStrPool() const {
return const_cast<ManagedStringPool *>(&ManagedStrPool);

2
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
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@ -32,7 +32,7 @@ private:
public:
NVPTXReplaceImageHandles();
bool runOnMachineFunction(MachineFunction &MF);
bool runOnMachineFunction(MachineFunction &MF) override;
private:
bool processInstr(MachineInstr &MI);
void replaceImageHandle(MachineOperand &Op, MachineFunction &MF);

16
lib/Target/NVPTX/NVPTXSection.h
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@ -31,16 +31,16 @@ public:
/// Override this as NVPTX has its own way of printing switching
/// to a section.
virtual void PrintSwitchToSection(const MCAsmInfo &MAI,
raw_ostream &OS,
const MCExpr *Subsection) const {}
void PrintSwitchToSection(const MCAsmInfo &MAI,
raw_ostream &OS,
const MCExpr *Subsection) const override {}
/// Base address of PTX sections is zero.
virtual bool isBaseAddressKnownZero() const { return true; }
virtual bool UseCodeAlign() const { return false; }
virtual bool isVirtualSection() const { return false; }
virtual std::string getLabelBeginName() const { return ""; }
virtual std::string getLabelEndName() const { return ""; }
bool isBaseAddressKnownZero() const override { return true; }
bool UseCodeAlign() const override { return false; }
bool isVirtualSection() const override { return false; }
std::string getLabelBeginName() const override { return ""; }
std::string getLabelEndName() const override { return ""; }
};
} // end namespace llvm

14
lib/Target/NVPTX/NVPTXTargetMachine.cpp
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@ -115,14 +115,14 @@ public:
return getTM<NVPTXTargetMachine>();
}
virtual void addIRPasses();
virtual bool addInstSelector();
virtual bool addPreRegAlloc();
virtual bool addPostRegAlloc();
void addIRPasses() override;
bool addInstSelector() override;
bool addPreRegAlloc() override;
bool addPostRegAlloc() override;
virtual FunctionPass *createTargetRegisterAllocator(bool) override;
virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
FunctionPass *createTargetRegisterAllocator(bool) override;
void addFastRegAlloc(FunctionPass *RegAllocPass) override;
void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
};
} // end anonymous namespace

24
lib/Target/NVPTX/NVPTXTargetMachine.h
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@ -51,22 +51,22 @@ public:
const TargetOptions &Options, Reloc::Model RM,
CodeModel::Model CM, CodeGenOpt::Level OP, bool is64bit);
virtual const TargetFrameLowering *getFrameLowering() const {
const TargetFrameLowering *getFrameLowering() const override {
return &FrameLowering;
}
virtual const NVPTXInstrInfo *getInstrInfo() const { return &InstrInfo; }
virtual const DataLayout *getDataLayout() const { return &DL; }
virtual const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
const NVPTXInstrInfo *getInstrInfo() const override { return &InstrInfo; }
const DataLayout *getDataLayout() const override { return &DL; }
const NVPTXSubtarget *getSubtargetImpl() const override { return &Subtarget; }
virtual const NVPTXRegisterInfo *getRegisterInfo() const {
const NVPTXRegisterInfo *getRegisterInfo() const override {
return &(InstrInfo.getRegisterInfo());
}
virtual NVPTXTargetLowering *getTargetLowering() const {
NVPTXTargetLowering *getTargetLowering() const override {
return const_cast<NVPTXTargetLowering *>(&TLInfo);
}
virtual const TargetSelectionDAGInfo *getSelectionDAGInfo() const {
const TargetSelectionDAGInfo *getSelectionDAGInfo() const override {
return &TSInfo;
}
@ -79,17 +79,17 @@ public:
return const_cast<ManagedStringPool *>(&ManagedStrPool);
}
virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
// Emission of machine code through JITCodeEmitter is not supported.
virtual bool addPassesToEmitMachineCode(PassManagerBase &, JITCodeEmitter &,
bool = true) {
bool addPassesToEmitMachineCode(PassManagerBase &, JITCodeEmitter &,
bool = true) override {
return true;
}
// Emission of machine code through MCJIT is not supported.
virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_ostream &,
bool = true) {
bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_ostream &,
bool = true) override {
return true;
}

6
lib/Target/NVPTX/NVVMReflect.cpp
View File

@ -65,8 +65,10 @@ public:
}
}
void getAnalysisUsage(AnalysisUsage &AU) const { AU.setPreservesAll(); }
virtual bool runOnModule(Module &);
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.setPreservesAll();
}
bool runOnModule(Module &) override;
void setVarMap();
};