6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-04-12 23:37:33 +00:00
Code Issues Projects Releases Wiki Activity

Adjust rules for building .inc files due to Reid's changes of Makefile.rules

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@17169 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Misha Brukman 2004-10-22 22:16:24 +00:00
parent 40a955ab05
commit 6b9ae58c52
2 changed files with 10 additions and 64 deletions
lib/Target
Sparc
Makefile
SparcV8
Makefile

37
lib/Target/Sparc/Makefile

@ -8,39 +8,12 @@
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = sparcv8
include $(LEVEL)/Makefile.common
TDFILES := $(wildcard $(SourceDir)/*.td) $(SourceDir)/../../Target.td
TDFILE := $(SourceDir)/SparcV8.td
TARGET = SparcV8
# Make sure that tblgen is run, first thing.
$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
SparcV8GenInstrInfo.inc SparcV8GenCodeEmitter.inc
BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
SparcV8GenInstrInfo.inc SparcV8GenCodeEmitter.inc
SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-enums -o $@
include $(LEVEL)/Makefile.common
SparcV8GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register information header with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-desc-header -o $@
SparcV8GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register information implementation with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-desc -o $@
SparcV8GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-enums -o $@
SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
SparcV8GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td code emitter with tblgen"
$(VERB) $(TBLGEN) -I $(SourceDir) $(TDFILE) -gen-emitter -o $@
clean::
$(VERB) rm -f *.inc

37
lib/Target/SparcV8/Makefile

@ -8,39 +8,12 @@
##===----------------------------------------------------------------------===##
LEVEL = ../../../..
LIBRARYNAME = sparcv8
include $(LEVEL)/Makefile.common
TDFILES := $(wildcard $(SourceDir)/*.td) $(SourceDir)/../../Target.td
TDFILE := $(SourceDir)/SparcV8.td
TARGET = SparcV8
# Make sure that tblgen is run, first thing.
$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
SparcV8GenInstrInfo.inc SparcV8GenCodeEmitter.inc
BUILT_SOURCES = SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
SparcV8GenInstrInfo.inc SparcV8GenCodeEmitter.inc
SparcV8GenRegisterNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-enums -o $@
include $(LEVEL)/Makefile.common
SparcV8GenRegisterInfo.h.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register information header with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-desc-header -o $@
SparcV8GenRegisterInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td register information implementation with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-register-desc -o $@
SparcV8GenInstrNames.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction names with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-enums -o $@
SparcV8GenInstrInfo.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td instruction information with tblgen"
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $(TDFILE) -gen-instr-desc -o $@
SparcV8GenCodeEmitter.inc:: $(TDFILES) $(TBLGEN)
@echo "Building SparcV8.td code emitter with tblgen"
$(VERB) $(TBLGEN) -I $(SourceDir) $(TDFILE) -gen-emitter -o $@
clean::
$(VERB) rm -f *.inc