Fix the bahavior of the disassembler when decoding unpredictable mrs instructions on ARM. Now the diasassembler emmits warnings instead of errors.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155002 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Silviu Baranga 2012-04-18 14:09:07 +00:00
parent fa1ebc6abe
commit 6b9f97dd89
2 changed files with 33 additions and 5 deletions

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@ -4646,22 +4646,32 @@ def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
//
// Move to ARM core register from Special Register
def MRS : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
def MRS : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
"mrs", "\t$Rd, apsr", []> {
bits<4> Rd;
let Inst{23-16} = 0b00001111;
let Unpredictable{19-17} = 0b111;
let Inst{15-12} = Rd;
let Inst{7-4} = 0b0000;
let Inst{11-0} = 0b000000000000;
let Unpredictable{11-0} = 0b110100001111;
}
def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPR:$Rd, pred:$p)>, Requires<[IsARM]>;
def : InstAlias<"mrs${p} $Rd, cpsr", (MRS GPRnopc:$Rd, pred:$p)>, Requires<[IsARM]>;
def MRSsys : ABI<0b0001, (outs GPR:$Rd), (ins), NoItinerary,
// The MRSsys instruction is the MRS instruction from the ARM ARM,
// section B9.3.9, with the R bit set to 1.
def MRSsys : ABI<0b0001, (outs GPRnopc:$Rd), (ins), NoItinerary,
"mrs", "\t$Rd, spsr", []> {
bits<4> Rd;
let Inst{23-16} = 0b01001111;
let Unpredictable{19-16} = 0b1111;
let Inst{15-12} = Rd;
let Inst{7-4} = 0b0000;
let Inst{11-0} = 0b000000000000;
let Unpredictable{11-0} = 0b110100001111;
}
// Move from ARM core register to Special Register

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@ -0,0 +1,18 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& FileCheck %s
# CHECK: warning: potentially undefined
# CHECK: 0x00 0xf0 0x0f 0x01
0x00 0xf0 0x0f 0x01
# CHECK: warning: potentially undefined
# CHECK: 0x00 0xf0 0x4f 0x01
0x00 0xf0 0x4f 0x01
# CHECK: warning: potentially undefined
# CHECK: 0x0f 0x0d 0x01 0x01
0x0f 0x0d 0x01 0x01
# CHECK: warning: potentially undefined
# CHECK: 0x0f 0x0d 0x40 0x01
0x0f 0x0d 0x40 0x01