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Fix encoding of 32-bit integer instructions. Change names of operands and nodes.

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Remove unused classes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141757 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2011-10-12 00:56:06 +00:00
parent d0851aae51
commit 6baabc1dd0
1 changed files with 108 additions and 87 deletions
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195
lib/Target/Mips/MipsInstrInfo.td
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@ -286,56 +286,59 @@ class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt), FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
!strconcat(instr_asm, "\t$rs, $rt"), !strconcat(instr_asm, "\t$rs, $rt"),
[(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> { [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
let rd = 0;
let shamt = 0;
let isCommutable = isComm; let isCommutable = isComm;
} }
// Logical // Logical
let isCommutable = 1 in
class LogicNOR<bits<6> op, bits<6> func, string instr_asm>: class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c), FR<op, func, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt),
!strconcat(instr_asm, "\t$dst, $b, $c"), !strconcat(instr_asm, "\t$rd, $rs, $rt"),
[(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>; [(set CPURegs:$rd, (not (or CPURegs:$rs, CPURegs:$rt)))], IIAlu> {
let shamt = 0;
let isCommutable = 1;
}
// Shifts // Shifts
class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm, class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
SDNode OpNode>: SDNode OpNode>:
FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c), FR<0x00, func, (outs CPURegs:$rd), (ins CPURegs:$rt, shamt:$shamt),
!strconcat(instr_asm, "\t$dst, $b, $c"), !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
[(set CPURegs:$dst, (OpNode CPURegs:$b, (i32 immZExt5:$c)))], IIAlu> { [(set CPURegs:$rd, (OpNode CPURegs:$rt, (i32 immZExt5:$shamt)))], IIAlu> {
let rs = _rs; let rs = _rs;
} }
class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm, class LogicR_shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
SDNode OpNode>: SDNode OpNode>:
FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b), FR<0x00, func, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt),
!strconcat(instr_asm, "\t$dst, $b, $c"), !strconcat(instr_asm, "\t$rd, $rt, $rs"),
[(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> { [(set CPURegs:$rd, (OpNode CPURegs:$rt, CPURegs:$rs))], IIAlu> {
let shamt = _shamt; let shamt = isRotate;
} }
// Load Upper Imediate // Load Upper Imediate
class LoadUpper<bits<6> op, string instr_asm>: class LoadUpper<bits<6> op, string instr_asm>:
FI< op, FI<op, (outs CPURegs:$rt), (ins uimm16:$imm),
(outs CPURegs:$dst), !strconcat(instr_asm, "\t$rt, $imm"), [], IIAlu> {
(ins uimm16:$imm), let rs = 0;
!strconcat(instr_asm, "\t$dst, $imm"), }
[], IIAlu>;
// Memory Load/Store // Memory Load/Store
let canFoldAsLoad = 1 in let canFoldAsLoad = 1 in
class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
Operand MemOpnd, bit Pseudo>: Operand MemOpnd, bit Pseudo>:
FI<op, (outs RC:$dst), (ins MemOpnd:$addr), FI<op, (outs RC:$rt), (ins MemOpnd:$addr),
!strconcat(instr_asm, "\t$dst, $addr"), !strconcat(instr_asm, "\t$rt, $addr"),
[(set RC:$dst, (OpNode addr:$addr))], IILoad> { [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
let isPseudo = Pseudo; let isPseudo = Pseudo;
} }
class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC, class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
Operand MemOpnd, bit Pseudo>: Operand MemOpnd, bit Pseudo>:
FI<op, (outs), (ins RC:$dst, MemOpnd:$addr), FI<op, (outs), (ins RC:$rt, MemOpnd:$addr),
!strconcat(instr_asm, "\t$dst, $addr"), !strconcat(instr_asm, "\t$rt, $addr"),
[(OpNode RC:$dst, addr:$addr)], IIStore> { [(OpNode RC:$rt, addr:$addr)], IIStore> {
let isPseudo = Pseudo; let isPseudo = Pseudo;
} }
@ -402,7 +405,9 @@ class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt), FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
!strconcat(instr_asm, "\t$rd, $rs, $rt"), !strconcat(instr_asm, "\t$rd, $rs, $rt"),
[(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))], [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
IIAlu>; IIAlu> {
let shamt = 0;
}
class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od, class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
PatLeaf imm_type, RegisterClass RC>: PatLeaf imm_type, RegisterClass RC>:
@ -419,8 +424,12 @@ class JumpFJ<bits<6> op, string instr_asm>:
let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
class JumpFR<bits<6> op, bits<6> func, string instr_asm>: class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
FR<op, func, (outs), (ins CPURegs:$target), FR<op, func, (outs), (ins CPURegs:$rs),
!strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>; !strconcat(instr_asm, "\t$rs"), [(brind CPURegs:$rs)], IIBranch> {
let rt = 0;
let rd = 0;
let shamt = 0;
}
// Jump and Link (Call) // Jump and Link (Call)
let isCall=1, hasDelaySlot=1, let isCall=1, hasDelaySlot=1,
@ -432,76 +441,93 @@ let isCall=1, hasDelaySlot=1,
!strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)], !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
IIBranch>; IIBranch>;
let rd=31 in
class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>: class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
FR<op, func, (outs), (ins CPURegs:$rs, variable_ops), FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
!strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>; !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch> {
let rt = 0;
let rd = 31;
let shamt = 0;
}
class BranchLink<string instr_asm>: class BranchLink<string instr_asm>:
FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops), FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
!strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>; !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch> {
let rt = 0;
}
} }
// Mul, Div // Mul, Div
let Defs = [HI, LO] in { class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
let isCommutable = 1 in FR<0x00, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
class Mul<bits<6> func, string instr_asm, InstrItinClass itin>: !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b), let rd = 0;
!strconcat(instr_asm, "\t$a, $b"), [], itin>; let shamt = 0;
let isCommutable = 1;
let Defs = [HI, LO];
}
class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>: class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b), FR<0x00, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
!strconcat(instr_asm, "\t$$zero, $a, $b"), !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
[(op CPURegs:$a, CPURegs:$b)], itin>; [(op CPURegs:$rs, CPURegs:$rt)], itin> {
let rd = 0;
let shamt = 0;
let Defs = [HI, LO];
} }
// Move from Hi/Lo // Move from Hi/Lo
let shamt = 0 in {
let rs = 0, rt = 0 in
class MoveFromLOHI<bits<6> func, string instr_asm>: class MoveFromLOHI<bits<6> func, string instr_asm>:
FR<0x00, func, (outs CPURegs:$dst), (ins), FR<0x00, func, (outs CPURegs:$rd), (ins),
!strconcat(instr_asm, "\t$dst"), [], IIHiLo>; !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
let rs = 0;
let rt = 0;
let shamt = 0;
}
let rt = 0, rd = 0 in
class MoveToLOHI<bits<6> func, string instr_asm>: class MoveToLOHI<bits<6> func, string instr_asm>:
FR<0x00, func, (outs), (ins CPURegs:$src), FR<0x00, func, (outs), (ins CPURegs:$rs),
!strconcat(instr_asm, "\t$src"), [], IIHiLo>; !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
let rt = 0;
let rd = 0;
let shamt = 0;
} }
class EffectiveAddress<string instr_asm> : class EffectiveAddress<string instr_asm> :
FI<0x09, (outs CPURegs:$dst), (ins mem_ea:$addr), FI<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr),
instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>; instr_asm, [(set CPURegs:$rt, addr:$addr)], IIAlu>;
// Count Leading Ones/Zeros in Word // Count Leading Ones/Zeros in Word
class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>: class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src), FR<0x1c, func, (outs CPURegs:$rd), (ins CPURegs:$rs),
!strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>, !strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>,
Requires<[HasBitCount]> { Requires<[HasBitCount]> {
let shamt = 0; let shamt = 0;
let rt = rd; let rt = rd;
} }
// Sign Extend in Register. // Sign Extend in Register.
class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>: class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt>:
FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src), FR<0x3f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
!strconcat(instr_asm, "\t$dst, $src"), !strconcat(instr_asm, "\t$rd, $rt"),
[(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>; [(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> {
let rs = 0;
let shamt = sa;
let Predicates = [HasSEInReg];
}
// Byte Swap // Byte Swap
class ByteSwap<bits<6> func, string instr_asm>: class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>:
FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src), FR<0x1f, func, (outs CPURegs:$rd), (ins CPURegs:$rt),
!strconcat(instr_asm, "\t$dst, $src"), !strconcat(instr_asm, "\t$rd, $rt"),
[(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>; [(set CPURegs:$rd, (bswap CPURegs:$rt))], NoItinerary> {
let rs = 0;
// Conditional Move let shamt = sa;
class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>: let Predicates = [HasSwap];
FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T, }
CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
[], NoItinerary>;
// Read Hardware // Read Hardware
class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src), class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
"rdhwr\t$dst, $src", [], IIAlu> { "rdhwr\t$rt, $rd", [], IIAlu> {
let rs = 0; let rs = 0;
let shamt = 0; let shamt = 0;
} }
@ -712,36 +738,31 @@ let Uses = [LO] in
def MFLO : MoveFromLOHI<0x12, "mflo">; def MFLO : MoveFromLOHI<0x12, "mflo">;
/// Sign Ext In Register Instructions. /// Sign Ext In Register Instructions.
let Predicates = [HasSEInReg] in { def SEB : SignExtInReg<0x10, "seb", i8>;
let shamt = 0x10, rs = 0 in def SEH : SignExtInReg<0x18, "seh", i16>;
def SEB : SignExtInReg<0x21, "seb", i8>;
let shamt = 0x18, rs = 0 in
def SEH : SignExtInReg<0x20, "seh", i16>;
}
/// Count Leading /// Count Leading
def CLZ : CountLeading<0b100000, "clz", def CLZ : CountLeading<0x20, "clz",
[(set CPURegs:$dst, (ctlz CPURegs:$src))]>; [(set CPURegs:$rd, (ctlz CPURegs:$rs))]>;
def CLO : CountLeading<0b100001, "clo", def CLO : CountLeading<0x21, "clo",
[(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>; [(set CPURegs:$rd, (ctlz (not CPURegs:$rs)))]>;
/// Byte Swap /// Byte Swap
let Predicates = [HasSwap] in { def WSBW : ByteSwap<0x20, 0x2, "wsbw">;
let shamt = 0x3, rs = 0 in
def WSBW : ByteSwap<0x20, "wsbw">;
}
// Conditional moves: // Conditional moves:
// These instructions are expanded in // These instructions are expanded in
// MipsISelLowering::EmitInstrWithCustomInserter if target does not have // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
// conditional move instructions. // conditional move instructions.
// flag:int, data:int // flag:int, data:int
let usesCustomInserter = 1, shamt = 0, Constraints = "$F = $dst" in class CondMovIntInt<bits<6> funct, string instr_asm> :
class CondMovIntInt<bits<6> funct, string instr_asm> : FR<0, funct, (outs CPURegs:$rd),
FR<0, funct, (outs CPURegs:$dst), (ins CPURegs:$rs, CPURegs:$rt, CPURegs:$F),
(ins CPURegs:$T, CPURegs:$cond, CPURegs:$F), !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
!strconcat(instr_asm, "\t$dst, $T, $cond"), [], NoItinerary>; let shamt = 0;
let usesCustomInserter = 1;
let Constraints = "$F = $rd";
}
def MOVZ_I : CondMovIntInt<0x0a, "movz">; def MOVZ_I : CondMovIntInt<0x0a, "movz">;
def MOVN_I : CondMovIntInt<0x0b, "movn">; def MOVN_I : CondMovIntInt<0x0b, "movn">;
@ -754,13 +775,13 @@ let addr=0 in
// instructions. The same not happens for stack address copies, so an // instructions. The same not happens for stack address copies, so an
// add op with mem ComplexPattern is used and the stack address copy // add op with mem ComplexPattern is used and the stack address copy
// can be matched. It's similar to Sparc LEA_ADDRi // can be matched. It's similar to Sparc LEA_ADDRi
def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, $addr">; def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr">;
// DynAlloc node points to dynamically allocated stack space. // DynAlloc node points to dynamically allocated stack space.
// $sp is added to the list of implicitly used registers to prevent dead code // $sp is added to the list of implicitly used registers to prevent dead code
// elimination from removing instructions that modify $sp. // elimination from removing instructions that modify $sp.
let Uses = [SP] in let Uses = [SP] in
def DynAlloc : EffectiveAddress<"addiu\t$dst, $addr">; def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr">;
// MADD*/MSUB* // MADD*/MSUB*
def MADD : MArithR<0, "madd", MipsMAdd, 1>; def MADD : MArithR<0, "madd", MipsMAdd, 1>;