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R600/SI: Fix spilling of m0 register

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If we have spilled the value of the m0 register, then we need to restore
it with v_readlane_b32 to a regular sgpr, because v_readlane_b32 can't
write to m0.

v_readlane_b32 can't write to m0, so

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@222036 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard 2014-11-14 20:43:26 +00:00
parent f6c436e9d7
commit 6beb81daa5
2 changed files with 43 additions and 1 deletions
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10
lib/Target/R600/SIRegisterInfo.cpp
View File

@ -145,6 +145,7 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(),
&AMDGPU::SGPR_32RegClass, i);
bool isM0 = SubReg == AMDGPU::M0;
struct SIMachineFunctionInfo::SpilledReg Spill =
MFI->getSpilledReg(MF, Index, i);
@ -153,10 +154,17 @@ void SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
Ctx.emitError("Ran out of VGPRs for spilling SGPR");
}
if (isM0) {
SubReg = RS->scavengeRegister(&AMDGPU::SGPR_32RegClass, MI, 0);
}
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READLANE_B32), SubReg)
.addReg(Spill.VGPR)
.addImm(Spill.Lane);
if (isM0) {
BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
.addReg(SubReg);
}
}
TII->insertNOPs(MI, 3);
MI->eraseFromParent();

34
test/CodeGen/R600/m0-spill.ll Normal file
View File

@ -0,0 +1,34 @@
; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s
@lds = external addrspace(3) global [64 x float]
; CHECK-LABEL: {{^}}main:
; CHECK-NOT: v_readlane_b32 m0
define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg) "ShaderType"="0" {
main_body:
%4 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
%cmp = fcmp ueq float 0.0, %4
br i1 %cmp, label %if, label %else
if:
%lds_ptr = getelementptr [64 x float] addrspace(3)* @lds, i32 0, i32 0
%lds_data = load float addrspace(3)* %lds_ptr
br label %endif
else:
%interp = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
br label %endif
endif:
%export = phi float [%lds_data, %if], [%interp, %else]
%5 = call i32 @llvm.SI.packf16(float %export, float %export)
%6 = bitcast i32 %5 to float
call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %6, float %6, float %6, float %6)
ret void
}
declare float @llvm.SI.fs.constant(i32, i32, i32) readnone
declare i32 @llvm.SI.packf16(float, float) readnone
declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)