6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2025-08-09 11:25:55 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Refactor VOP1 instruction defs

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219253 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2014-10-07 23:51:34 +00:00
parent 99ff4a2dba
commit 6bf4c41242
3 changed files with 96 additions and 72 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
lib/Target/R600/SIInstrFormats.td
View File

@@ -60,6 +60,15 @@ class Enc64 {
int Size = 8; int Size = 8;
} }
class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let VOP1 = 1;
}
class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> : class VOP3Common <dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern> { InstSI <outs, ins, asm, pattern> {
@@ -485,14 +494,8 @@ class EXPe : Enc64 {
let Uses = [EXEC] in { let Uses = [EXEC] in {
class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern>, VOP1e<op> { VOP1Common <outs, ins, asm, pattern>,
VOP1e<op>;
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let UseNamedOperandTable = 1;
let VOP1 = 1;
}
class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> :
InstSI <outs, ins, asm, pattern>, VOP2e<op> { InstSI <outs, ins, asm, pattern>, VOP2e<op> {

36
lib/Target/R600/SIInstrInfo.td
View File

@@ -7,6 +7,16 @@
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
class vop {
field bits<9> SI3;
}
class vop1 <bits<8> si> : vop {
field bits<8> SI = si;
field bits<9> SI3 = {1, 1, si{6-0}};
}
// Execpt for the NONE field, this must be kept in sync with the SISubtarget enum // Execpt for the NONE field, this must be kept in sync with the SISubtarget enum
// in AMDGPUMCInstLower.h // in AMDGPUMCInstLower.h
def SISubtarget { def SISubtarget {
@@ -585,6 +595,20 @@ class AtomicNoRet <string noRetOp, bit isRet> {
bit IsRet = isRet; bit IsRet = isRet;
} }
class VOP1_Pseudo <dag outs, dag ins, list<dag> pattern, string opName> :
VOP1Common <outs, ins, "", pattern>,
SIMCInstr<opName, SISubtarget.NONE> {
let isPseudo = 1;
}
multiclass VOP1_m <vop1 op, dag outs, dag ins, string asm, list<dag> pattern,
string opName> {
def "" : VOP1_Pseudo <outs, ins, pattern, opName>;
def _si : VOP1<op.SI, outs, ins, asm, []>,
SIMCInstr <opName, SISubtarget.SI>;
}
class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> { class VOP3DisableFields <bit HasSrc1, bit HasSrc2, bit HasModifiers> {
bits<2> src0_modifiers = !if(HasModifiers, ?, 0); bits<2> src0_modifiers = !if(HasModifiers, ?, 0);
@@ -619,14 +643,12 @@ multiclass VOP3_m <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern,
} }
multiclass VOP3_1_m <bits<8> op, dag outs, dag ins, string asm, multiclass VOP3_1_m <vop op, dag outs, dag ins, string asm,
list<dag> pattern, string opName, bit HasMods = 1> { list<dag> pattern, string opName, bit HasMods = 1> {
def "" : VOP3_Pseudo <outs, ins, pattern, opName>; def "" : VOP3_Pseudo <outs, ins, pattern, opName>;
def _si : VOP3_Real_si < def _si : VOP3_Real_si <op.SI3, outs, ins, asm, opName>,
{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
outs, ins, asm, opName>,
VOP3DisableFields<0, 0, HasMods>; VOP3DisableFields<0, 0, HasMods>;
} }
@@ -674,17 +696,17 @@ multiclass VOP3_C_m <bits<8> op, dag outs, dag ins, string asm,
} }
} }
multiclass VOP1_Helper <bits<8> op, string opName, dag outs, multiclass VOP1_Helper <vop1 op, string opName, dag outs,
dag ins32, string asm32, list<dag> pat32, dag ins32, string asm32, list<dag> pat32,
dag ins64, string asm64, list<dag> pat64, dag ins64, string asm64, list<dag> pat64,
bit HasMods> { bit HasMods> {
def _e32 : VOP1 <op, outs, ins32, opName#asm32, pat32>, VOP<opName>; def _e32 : VOP1 <op.SI, outs, ins32, opName#asm32, pat32>, VOP<opName>;
defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>; defm _e64 : VOP3_1_m <op, outs, ins64, opName#"_e64"#asm64, pat64, opName, HasMods>;
} }
multiclass VOP1Inst <bits<8> op, string opName, VOPProfile P, multiclass VOP1Inst <vop1 op, string opName, VOPProfile P,
SDPatternOperator node = null_frag> : VOP1_Helper < SDPatternOperator node = null_frag> : VOP1_Helper <
op, opName, P.Outs, op, opName, P.Outs,
P.Ins32, P.Asm32, [], P.Ins32, P.Asm32, [],

113
lib/Target/R600/SIInstructions.td
View File

@@ -1128,7 +1128,7 @@ def FLAT_STORE_DWORDX3 : FLAT_Store_Helper <
//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; //def V_NOP : VOP1_ <0x00000000, "V_NOP", []>;
let isMoveImm = 1 in { let isMoveImm = 1 in {
defm V_MOV_B32 : VOP1Inst <0x00000001, "V_MOV_B32", VOP_I32_I32>; defm V_MOV_B32 : VOP1Inst <vop1<0x1>, "V_MOV_B32", VOP_I32_I32>;
} // End isMoveImm = 1 } // End isMoveImm = 1
let Uses = [EXEC] in { let Uses = [EXEC] in {
@@ -1143,134 +1143,133 @@ def V_READFIRSTLANE_B32 : VOP1 <
} }
defm V_CVT_I32_F64 : VOP1Inst <0x00000003, "V_CVT_I32_F64", defm V_CVT_I32_F64 : VOP1Inst <vop1<0x3>, "V_CVT_I32_F64",
VOP_I32_F64, fp_to_sint VOP_I32_F64, fp_to_sint
>; >;
defm V_CVT_F64_I32 : VOP1Inst <0x00000004, "V_CVT_F64_I32", defm V_CVT_F64_I32 : VOP1Inst <vop1<0x4>, "V_CVT_F64_I32",
VOP_F64_I32, sint_to_fp VOP_F64_I32, sint_to_fp
>; >;
defm V_CVT_F32_I32 : VOP1Inst <0x00000005, "V_CVT_F32_I32", defm V_CVT_F32_I32 : VOP1Inst <vop1<0x5>, "V_CVT_F32_I32",
VOP_F32_I32, sint_to_fp VOP_F32_I32, sint_to_fp
>; >;
defm V_CVT_F32_U32 : VOP1Inst <0x00000006, "V_CVT_F32_U32", defm V_CVT_F32_U32 : VOP1Inst <vop1<0x6>, "V_CVT_F32_U32",
VOP_F32_I32, uint_to_fp VOP_F32_I32, uint_to_fp
>; >;
defm V_CVT_U32_F32 : VOP1Inst <0x00000007, "V_CVT_U32_F32", defm V_CVT_U32_F32 : VOP1Inst <vop1<0x7>, "V_CVT_U32_F32",
VOP_I32_F32, fp_to_uint VOP_I32_F32, fp_to_uint
>; >;
defm V_CVT_I32_F32 : VOP1Inst <0x00000008, "V_CVT_I32_F32", defm V_CVT_I32_F32 : VOP1Inst <vop1<0x8>, "V_CVT_I32_F32",
VOP_I32_F32, fp_to_sint VOP_I32_F32, fp_to_sint
>; >;
defm V_MOV_FED_B32 : VOP1Inst <0x00000009, "V_MOV_FED_B32", VOP_I32_I32>; defm V_MOV_FED_B32 : VOP1Inst <vop1<0x9>, "V_MOV_FED_B32", VOP_I32_I32>;
defm V_CVT_F16_F32 : VOP1Inst <0x0000000a, "V_CVT_F16_F32", defm V_CVT_F16_F32 : VOP1Inst <vop1<0xa>, "V_CVT_F16_F32",
VOP_I32_F32, fp_to_f16 VOP_I32_F32, fp_to_f16
>; >;
defm V_CVT_F32_F16 : VOP1Inst <0x0000000b, "V_CVT_F32_F16", defm V_CVT_F32_F16 : VOP1Inst <vop1<0xb>, "V_CVT_F32_F16",
VOP_F32_I32, f16_to_fp VOP_F32_I32, f16_to_fp
>; >;
//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; //defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>;
//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; //defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>;
//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; //defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>;
defm V_CVT_F32_F64 : VOP1Inst <0x0000000f, "V_CVT_F32_F64", defm V_CVT_F32_F64 : VOP1Inst <vop1<0xf>, "V_CVT_F32_F64",
VOP_F32_F64, fround VOP_F32_F64, fround
>; >;
defm V_CVT_F64_F32 : VOP1Inst <0x00000010, "V_CVT_F64_F32", defm V_CVT_F64_F32 : VOP1Inst <vop1<0x10>, "V_CVT_F64_F32",
VOP_F64_F32, fextend VOP_F64_F32, fextend
>; >;
defm V_CVT_F32_UBYTE0 : VOP1Inst <0x00000011, "V_CVT_F32_UBYTE0", defm V_CVT_F32_UBYTE0 : VOP1Inst <vop1<0x11>, "V_CVT_F32_UBYTE0",
VOP_F32_I32, AMDGPUcvt_f32_ubyte0 VOP_F32_I32, AMDGPUcvt_f32_ubyte0
>; >;
defm V_CVT_F32_UBYTE1 : VOP1Inst <0x00000012, "V_CVT_F32_UBYTE1", defm V_CVT_F32_UBYTE1 : VOP1Inst <vop1<0x12>, "V_CVT_F32_UBYTE1",
VOP_F32_I32, AMDGPUcvt_f32_ubyte1 VOP_F32_I32, AMDGPUcvt_f32_ubyte1
>; >;
defm V_CVT_F32_UBYTE2 : VOP1Inst <0x00000013, "V_CVT_F32_UBYTE2", defm V_CVT_F32_UBYTE2 : VOP1Inst <vop1<0x13>, "V_CVT_F32_UBYTE2",
VOP_F32_I32, AMDGPUcvt_f32_ubyte2 VOP_F32_I32, AMDGPUcvt_f32_ubyte2
>; >;
defm V_CVT_F32_UBYTE3 : VOP1Inst <0x00000014, "V_CVT_F32_UBYTE3", defm V_CVT_F32_UBYTE3 : VOP1Inst <vop1<0x14>, "V_CVT_F32_UBYTE3",
VOP_F32_I32, AMDGPUcvt_f32_ubyte3 VOP_F32_I32, AMDGPUcvt_f32_ubyte3
>; >;
defm V_CVT_U32_F64 : VOP1Inst <0x00000015, "V_CVT_U32_F64", defm V_CVT_U32_F64 : VOP1Inst <vop1<0x15>, "V_CVT_U32_F64",
VOP_I32_F64, fp_to_uint VOP_I32_F64, fp_to_uint
>; >;
defm V_CVT_F64_U32 : VOP1Inst <0x00000016, "V_CVT_F64_U32", defm V_CVT_F64_U32 : VOP1Inst <vop1<0x16>, "V_CVT_F64_U32",
VOP_F64_I32, uint_to_fp VOP_F64_I32, uint_to_fp
>; >;
defm V_FRACT_F32 : VOP1Inst <0x00000020, "V_FRACT_F32", defm V_FRACT_F32 : VOP1Inst <vop1<0x20>, "V_FRACT_F32",
VOP_F32_F32, AMDGPUfract VOP_F32_F32, AMDGPUfract
>; >;
defm V_TRUNC_F32 : VOP1Inst <0x00000021, "V_TRUNC_F32", defm V_TRUNC_F32 : VOP1Inst <vop1<0x21>, "V_TRUNC_F32",
VOP_F32_F32, ftrunc VOP_F32_F32, ftrunc
>; >;
defm V_CEIL_F32 : VOP1Inst <0x00000022, "V_CEIL_F32", defm V_CEIL_F32 : VOP1Inst <vop1<0x22>, "V_CEIL_F32",
VOP_F32_F32, fceil VOP_F32_F32, fceil
>; >;
defm V_RNDNE_F32 : VOP1Inst <0x00000023, "V_RNDNE_F32", defm V_RNDNE_F32 : VOP1Inst <vop1<0x23>, "V_RNDNE_F32",
VOP_F32_F32, frint VOP_F32_F32, frint
>; >;
defm V_FLOOR_F32 : VOP1Inst <0x00000024, "V_FLOOR_F32", defm V_FLOOR_F32 : VOP1Inst <vop1<0x24>, "V_FLOOR_F32",
VOP_F32_F32, ffloor VOP_F32_F32, ffloor
>; >;
defm V_EXP_F32 : VOP1Inst <0x00000025, "V_EXP_F32", defm V_EXP_F32 : VOP1Inst <vop1<0x25>, "V_EXP_F32",
VOP_F32_F32, fexp2 VOP_F32_F32, fexp2
>; >;
defm V_LOG_CLAMP_F32 : VOP1Inst <0x00000026, "V_LOG_CLAMP_F32", VOP_F32_F32>; defm V_LOG_CLAMP_F32 : VOP1Inst <vop1<0x26>, "V_LOG_CLAMP_F32", VOP_F32_F32>;
defm V_LOG_F32 : VOP1Inst <0x00000027, "V_LOG_F32", defm V_LOG_F32 : VOP1Inst <vop1<0x27>, "V_LOG_F32",
VOP_F32_F32, flog2 VOP_F32_F32, flog2
>; >;
defm V_RCP_CLAMP_F32 : VOP1Inst <0x00000028, "V_RCP_CLAMP_F32", VOP_F32_F32>; defm V_RCP_CLAMP_F32 : VOP1Inst <vop1<0x28>, "V_RCP_CLAMP_F32", VOP_F32_F32>;
defm V_RCP_LEGACY_F32 : VOP1Inst <0x00000029, "V_RCP_LEGACY_F32", VOP_F32_F32>; defm V_RCP_LEGACY_F32 : VOP1Inst <vop1<0x29>, "V_RCP_LEGACY_F32", VOP_F32_F32>;
defm V_RCP_F32 : VOP1Inst <0x0000002a, "V_RCP_F32", defm V_RCP_F32 : VOP1Inst <vop1<0x2a>, "V_RCP_F32",
VOP_F32_F32, AMDGPUrcp VOP_F32_F32, AMDGPUrcp
>; >;
defm V_RCP_IFLAG_F32 : VOP1Inst <0x0000002b, "V_RCP_IFLAG_F32", VOP_F32_F32>; defm V_RCP_IFLAG_F32 : VOP1Inst <vop1<0x2b>, "V_RCP_IFLAG_F32", VOP_F32_F32>;
defm V_RSQ_CLAMP_F32 : VOP1Inst <0x0000002c, "V_RSQ_CLAMP_F32", defm V_RSQ_CLAMP_F32 : VOP1Inst <vop1<0x2c>, "V_RSQ_CLAMP_F32",
VOP_F32_F32, AMDGPUrsq_clamped VOP_F32_F32, AMDGPUrsq_clamped
>; >;
defm V_RSQ_LEGACY_F32 : VOP1Inst < defm V_RSQ_LEGACY_F32 : VOP1Inst <vop1<0x2d>, "V_RSQ_LEGACY_F32",
0x0000002d, "V_RSQ_LEGACY_F32",
VOP_F32_F32, AMDGPUrsq_legacy VOP_F32_F32, AMDGPUrsq_legacy
>; >;
defm V_RSQ_F32 : VOP1Inst <0x0000002e, "V_RSQ_F32", defm V_RSQ_F32 : VOP1Inst <vop1<0x2e>, "V_RSQ_F32",
VOP_F32_F32, AMDGPUrsq VOP_F32_F32, AMDGPUrsq
>; >;
defm V_RCP_F64 : VOP1Inst <0x0000002f, "V_RCP_F64", defm V_RCP_F64 : VOP1Inst <vop1<0x2f>, "V_RCP_F64",
VOP_F64_F64, AMDGPUrcp VOP_F64_F64, AMDGPUrcp
>; >;
defm V_RCP_CLAMP_F64 : VOP1Inst <0x00000030, "V_RCP_CLAMP_F64", VOP_F64_F64>; defm V_RCP_CLAMP_F64 : VOP1Inst <vop1<0x30>, "V_RCP_CLAMP_F64", VOP_F64_F64>;
defm V_RSQ_F64 : VOP1Inst <0x00000031, "V_RSQ_F64", defm V_RSQ_F64 : VOP1Inst <vop1<0x31>, "V_RSQ_F64",
VOP_F64_F64, AMDGPUrsq VOP_F64_F64, AMDGPUrsq
>; >;
defm V_RSQ_CLAMP_F64 : VOP1Inst <0x00000032, "V_RSQ_CLAMP_F64", defm V_RSQ_CLAMP_F64 : VOP1Inst <vop1<0x32>, "V_RSQ_CLAMP_F64",
VOP_F64_F64, AMDGPUrsq_clamped VOP_F64_F64, AMDGPUrsq_clamped
>; >;
defm V_SQRT_F32 : VOP1Inst <0x00000033, "V_SQRT_F32", defm V_SQRT_F32 : VOP1Inst <vop1<0x33>, "V_SQRT_F32",
VOP_F32_F32, fsqrt VOP_F32_F32, fsqrt
>; >;
defm V_SQRT_F64 : VOP1Inst <0x00000034, "V_SQRT_F64", defm V_SQRT_F64 : VOP1Inst <vop1<0x34>, "V_SQRT_F64",
VOP_F64_F64, fsqrt VOP_F64_F64, fsqrt
>; >;
defm V_SIN_F32 : VOP1Inst <0x00000035, "V_SIN_F32", defm V_SIN_F32 : VOP1Inst <vop1<0x35>, "V_SIN_F32",
VOP_F32_F32, AMDGPUsin VOP_F32_F32, AMDGPUsin
>; >;
defm V_COS_F32 : VOP1Inst <0x00000036, "V_COS_F32", defm V_COS_F32 : VOP1Inst <vop1<0x36>, "V_COS_F32",
VOP_F32_F32, AMDGPUcos VOP_F32_F32, AMDGPUcos
>; >;
defm V_NOT_B32 : VOP1Inst <0x00000037, "V_NOT_B32", VOP_I32_I32>; defm V_NOT_B32 : VOP1Inst <vop1<0x37>, "V_NOT_B32", VOP_I32_I32>;
defm V_BFREV_B32 : VOP1Inst <0x00000038, "V_BFREV_B32", VOP_I32_I32>; defm V_BFREV_B32 : VOP1Inst <vop1<0x38>, "V_BFREV_B32", VOP_I32_I32>;
defm V_FFBH_U32 : VOP1Inst <0x00000039, "V_FFBH_U32", VOP_I32_I32>; defm V_FFBH_U32 : VOP1Inst <vop1<0x39>, "V_FFBH_U32", VOP_I32_I32>;
defm V_FFBL_B32 : VOP1Inst <0x0000003a, "V_FFBL_B32", VOP_I32_I32>; defm V_FFBL_B32 : VOP1Inst <vop1<0x3a>, "V_FFBL_B32", VOP_I32_I32>;
defm V_FFBH_I32 : VOP1Inst <0x0000003b, "V_FFBH_I32", VOP_I32_I32>; defm V_FFBH_I32 : VOP1Inst <vop1<0x3b>, "V_FFBH_I32", VOP_I32_I32>;
//defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "V_FREXP_EXP_I32_F64", VOP_I32_F32>; //defm V_FREXP_EXP_I32_F64 : VOPInst <0x0000003c, "V_FREXP_EXP_I32_F64", VOP_I32_F32>;
defm V_FREXP_MANT_F64 : VOP1Inst <0x0000003d, "V_FREXP_MANT_F64", VOP_F64_F64>; defm V_FREXP_MANT_F64 : VOP1Inst <vop1<0x3d>, "V_FREXP_MANT_F64", VOP_F64_F64>;
defm V_FRACT_F64 : VOP1Inst <0x0000003e, "V_FRACT_F64", VOP_F64_F64>; defm V_FRACT_F64 : VOP1Inst <vop1<0x3e>, "V_FRACT_F64", VOP_F64_F64>;
//defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "V_FREXP_EXP_I32_F32", VOP_I32_F32>; //defm V_FREXP_EXP_I32_F32 : VOPInst <0x0000003f, "V_FREXP_EXP_I32_F32", VOP_I32_F32>;
defm V_FREXP_MANT_F32 : VOP1Inst <0x00000040, "V_FREXP_MANT_F32", VOP_F32_F32>; defm V_FREXP_MANT_F32 : VOP1Inst <vop1<0x40>, "V_FREXP_MANT_F32", VOP_F32_F32>;
//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; //def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>;
defm V_MOVRELD_B32 : VOP1Inst <0x00000042, "V_MOVRELD_B32", VOP_I32_I32>; defm V_MOVRELD_B32 : VOP1Inst <vop1<0x42>, "V_MOVRELD_B32", VOP_I32_I32>;
defm V_MOVRELS_B32 : VOP1Inst <0x00000043, "V_MOVRELS_B32", VOP_I32_I32>; defm V_MOVRELS_B32 : VOP1Inst <vop1<0x43>, "V_MOVRELS_B32", VOP_I32_I32>;
defm V_MOVRELSD_B32 : VOP1Inst <0x00000044, "V_MOVRELSD_B32", VOP_I32_I32>; defm V_MOVRELSD_B32 : VOP1Inst <vop1<0x44>, "V_MOVRELSD_B32", VOP_I32_I32>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
@@ -2866,16 +2865,16 @@ def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>;
let SubtargetPredicate = isCI in { let SubtargetPredicate = isCI in {
// Sea island new arithmetic instructinos // Sea island new arithmetic instructinos
defm V_TRUNC_F64 : VOP1Inst <0x00000017, "V_TRUNC_F64", defm V_TRUNC_F64 : VOP1Inst <vop1<0x17>, "V_TRUNC_F64",
VOP_F64_F64, ftrunc VOP_F64_F64, ftrunc
>; >;
defm V_CEIL_F64 : VOP1Inst <0x00000018, "V_CEIL_F64", defm V_CEIL_F64 : VOP1Inst <vop1<0x18>, "V_CEIL_F64",
VOP_F64_F64, fceil VOP_F64_F64, fceil
>; >;
defm V_FLOOR_F64 : VOP1Inst <0x0000001A, "V_FLOOR_F64", defm V_FLOOR_F64 : VOP1Inst <vop1<0x1A>, "V_FLOOR_F64",
VOP_F64_F64, ffloor VOP_F64_F64, ffloor
>; >;
defm V_RNDNE_F64 : VOP1Inst <0x00000019, "V_RNDNE_F64", defm V_RNDNE_F64 : VOP1Inst <vop1<0x19>, "V_RNDNE_F64",
VOP_F64_F64, frint VOP_F64_F64, frint
>; >;