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R600: Implement isNarrowingProfitable.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204658 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Matt Arsenault
2014-03-24 19:43:31 +00:00
parent 03cd663eb1
commit 6c199d8212
3 changed files with 30 additions and 5 deletions
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10
lib/Target/R600/AMDGPUISelLowering.cpp
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@@ -273,6 +273,16 @@ bool AMDGPUTargetLowering::isTruncateFree(Type *Source, Type *Dest) const {
(Dest->getPrimitiveSizeInBits() % 32 == 0);
}
bool AMDGPUTargetLowering::isNarrowingProfitable(EVT SrcVT, EVT DestVT) const {
// There aren't really 64-bit registers, but pairs of 32-bit ones and only a
// limited number of native 64-bit operations. Shrinking an operation to fit
// in a single 32-bit register should always be helpful. As currently used,
// this is much less general than the name suggests, and is only used in
// places trying to reduce the sizes of loads. Shrinking loads to < 32-bits is
// not profitable, and may actually be harmful.
return SrcVT.getSizeInBits() > 32 && DestVT.getSizeInBits() == 32;
}
//===---------------------------------------------------------------------===//
// TargetLowering Callbacks
//===---------------------------------------------------------------------===//