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Add *_ldst_mult multiclasses to the ARM back-end. These will be used in the
future to separate out the ia, ib, da, db variants of the load/store multiple instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@118995 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling
parent
115a3dd066
commit
6c470b806f
@ -820,6 +820,18 @@ class AI3stdpo<dag oops, dag iops, Format f, InstrItinClass itin,
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}
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// addrmode4 instructions
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class AXI4<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> {
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bits<4> p;
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bits<16> regs;
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bits<4> Rn;
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let Inst{31-28} = p;
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let Inst{27-25} = 0b100;
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let Inst{22} = 0; // S bit
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let Inst{19-16} = Rn;
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let Inst{15-0} = regs;
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}
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class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin,
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string asm, string cstr, list<dag> pattern>
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: XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin,
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@ -1734,6 +1734,74 @@ def STRHT: AI3sthpo<(outs GPR:$base_wb),
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// Load / store multiple Instructions.
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//
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multiclass arm_ldst_mult<string asm, bit L_bit, Format f,
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InstrItinClass itin, InstrItinClass itin_upd> {
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def IA :
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AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeNone, f, itin,
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!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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}
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def IA_UPD :
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AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeUpd, f, itin_upd,
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!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 1; // No writeback
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let Inst{20} = L_bit;
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}
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def DA :
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AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeNone, f, itin,
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!strconcat(asm, "da${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b00; // Decrement After
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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}
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def DA_UPD :
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AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeUpd, f, itin_upd,
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!strconcat(asm, "da${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b00; // Decrement After
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let Inst{21} = 1; // No writeback
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let Inst{20} = L_bit;
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}
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def DB :
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AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeNone, f, itin,
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!strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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}
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def DB_UPD :
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AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeUpd, f, itin_upd,
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!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{21} = 1; // No writeback
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let Inst{20} = L_bit;
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}
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def IB :
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AXI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeNone, f, itin,
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!strconcat(asm, "ib${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b11; // Increment Before
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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}
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def IB_UPD :
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AXI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeUpd, f, itin_upd,
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!strconcat(asm, "ib${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b11; // Increment Before
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let Inst{21} = 1; // No writeback
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let Inst{20} = L_bit;
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}
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}
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
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@ -536,6 +536,19 @@ def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
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// Load / store multiple Instructions.
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//
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multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
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InstrItinClass itin_upd, bits<6> T1Enc,
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bit L_bit> {
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def IA :
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T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
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T1Encoding<T1Enc>;
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def IA_UPD :
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T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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itin_upd, !strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
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T1Encoding<T1Enc>;
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}
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// These require base address to be written back or one of the loaded regs.
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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@ -1283,6 +1283,70 @@ defm t2PLI : T2Ipl<0, 1, "pli">, Requires<[IsThumb2,HasV7]>;
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// Load / store multiple Instructions.
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//
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multiclass thumb2_ldst_mult<string asm, InstrItinClass itin,
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InstrItinClass itin_upd, bit L_bit> {
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def IA :
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T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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itin, !strconcat(asm, "${p}.w\t$Rn, $regs"), []> {
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bits<4> Rn;
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bits<16> regs;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b00;
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let Inst{24-23} = 0b01; // Increment After
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let Inst{22} = 0;
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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let Inst{19-16} = Rn;
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let Inst{15-0} = regs;
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}
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def IA_UPD :
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T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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itin_upd, !strconcat(asm, "${p}.w\t$Rn!, $regs"), "$Rn = $wb", []> {
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bits<4> Rn;
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bits<16> regs;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b00;
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let Inst{24-23} = 0b01; // Increment After
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let Inst{22} = 0;
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let Inst{21} = 1; // Writeback
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let Inst{20} = L_bit;
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let Inst{19-16} = Rn;
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let Inst{15-0} = regs;
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}
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def DB :
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T2XI<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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itin, !strconcat(asm, "db${p}.w\t$Rn, $regs"), []> {
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bits<4> Rn;
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bits<16> regs;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b00;
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{22} = 0;
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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let Inst{19-16} = Rn;
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let Inst{15-0} = regs;
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}
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def DB_UPD :
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T2XIt<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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itin_upd, !strconcat(asm, "db${p}.w\t$Rn, $regs"), "$Rn = $wb", []> {
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bits<4> Rn;
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bits<16> regs;
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let Inst{31-27} = 0b11101;
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let Inst{26-25} = 0b00;
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{22} = 0;
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let Inst{21} = 1; // Writeback
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let Inst{20} = L_bit;
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let Inst{19-16} = Rn;
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let Inst{15-0} = regs;
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}
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}
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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def t2LDM : T2XI<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
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@ -74,6 +74,78 @@ def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
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// Load / store multiple Instructions.
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//
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multiclass vfp_ldst_d_mult<string asm, bit L_bit,
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InstrItinClass itin, InstrItinClass itin_upd> {
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def IA :
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AXDI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeNone, itin,
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!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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}
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def IA_UPD :
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AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeUpd, itin_upd,
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!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 1; // Writeback
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let Inst{20} = L_bit;
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}
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def DB :
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AXDI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeNone, itin,
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!strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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}
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def DB_UPD :
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AXDI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeUpd, itin_upd,
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!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{21} = 1; // Writeback
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let Inst{20} = L_bit;
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}
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}
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multiclass vfp_ldst_s_mult<string asm, bit L_bit,
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InstrItinClass itin, InstrItinClass itin_upd> {
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def IA :
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AXSI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeNone, itin,
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!strconcat(asm, "${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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}
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def IA_UPD :
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AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeUpd, itin_upd,
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!strconcat(asm, "${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b01; // Increment After
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let Inst{21} = 1; // Writeback
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let Inst{20} = L_bit;
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}
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def DB :
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AXSI4<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeNone, itin,
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!strconcat(asm, "db${p}\t$Rn, $regs"), "", []> {
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{21} = 0; // No writeback
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let Inst{20} = L_bit;
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}
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def DB_UPD :
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AXSI4<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
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IndexModeUpd, itin_upd,
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!strconcat(asm, "db${p}\t$Rn!, $regs"), "$Rn = $wb", []> {
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let Inst{24-23} = 0b10; // Decrement Before
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let Inst{21} = 1; // Writeback
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let Inst{20} = L_bit;
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}
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}
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let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
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isCodeGenOnly = 1 in {
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def VLDMD : AXDI4<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p,
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