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Check for unallocated instruction encodings when disassembling Thumb Branch instructions (tBcc and t2Bcc).

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rdar://problem/9280470


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129471 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-13 21:35:49 +00:00
parent 471d73d5d3
commit 6c7e4147dc
3 changed files with 24 additions and 7 deletions
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16
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -3625,11 +3625,17 @@ bool ARMBasicMCBuilder::TryPredicateAndSBitModifier(MCInst& MI, unsigned Opcode,
// like ARM. // like ARM.
// //
// A8.6.16 B // A8.6.16 B
if (Name == "t2Bcc") // Check for undefined encodings.
MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 25, 22)))); unsigned cond;
else if (Name == "tBcc") if (Name == "t2Bcc") {
MI.addOperand(MCOperand::CreateImm(CondCode(slice(insn, 11, 8)))); if ((cond = slice(insn, 25, 22)) >= 14)
else return false;
MI.addOperand(MCOperand::CreateImm(CondCode(cond)));
} else if (Name == "tBcc") {
if ((cond = slice(insn, 11, 8)) == 14)
return false;
MI.addOperand(MCOperand::CreateImm(CondCode(cond)));
} else
MI.addOperand(MCOperand::CreateImm(ARMCC::AL)); MI.addOperand(MCOperand::CreateImm(ARMCC::AL));
} else { } else {
// ARM instructions get their condition field from Inst{31-28}. // ARM instructions get their condition field from Inst{31-28}.

11
test/MC/Disassembler/ARM/invalid-t2Bcc-thumb.txt Normal file
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@ -0,0 +1,11 @@
# RUN: llvm-mc --disassemble %s -triple=thumb-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=1894 Name=t2Bcc Format=ARM_FORMAT_THUMBFRM(25)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 1: 1: 1: 1| 0: 1: 1: 1| 1: 0: 1: 0| 1: 1: 1: 1| 1: 0: 0: 0| 1: 0: 1: 1| 0: 1: 0: 0| 0: 1: 0: 0|
# -------------------------------------------------------------------------------------------------
#
# A8.6.16 B
# if cond<3:1> == '111' then SEE "Related Encodings"
0xaf 0xf7 0x44 0x8b

4
test/MC/Disassembler/ARM/thumb-tests.txt
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@ -9,8 +9,8 @@
# CHECK: b #30 # CHECK: b #30
0x0f 0xe0 0x0f 0xe0
# CHECK: b.w #-16 # CHECK: bgt.w #-16
0xff 0xf7 0xf8 0xaf 0x3f 0xf7 0xf8 0xaf
# CHECK: bfi r2, r10, #0, #1 # CHECK: bfi r2, r10, #0, #1
0x6a 0xf3 0x00 0x02 0x6a 0xf3 0x00 0x02