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The two address pass cannot handle two addr instructions where one incoming

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value is a physreg and one is a virtreg.  For this reason, disable copy folding
entirely for physregs.  Also, use the new isMoveInstr target hook which gives us
folding of FP moves as well.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11700 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2004-02-22 04:44:58 +00:00
parent 7200c6b82a
commit 6d2fdcfb8a
2 changed files with 32 additions and 18 deletions
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25
lib/Target/X86/PeepholeOptimizer.cpp
View File

@ -15,6 +15,8 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include "Support/STLExtras.h"
@ -23,6 +25,7 @@ using namespace llvm;
namespace {
Statistic<> NumPHOpts("x86-peephole",
"Number of peephole optimization performed");
Statistic<> NumPHMoves("x86-peephole", "Number of peephole moves folded");
struct PH : public MachineFunctionPass {
virtual bool runOnMachineFunction(MachineFunction &MF);
@ -449,22 +452,26 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
bool Changed = false;
const TargetInstrInfo &TII = MBB.getParent()->getTarget().getInstrInfo();
// Scan the operands of this instruction. If any operands are
// register-register copies, replace the operand with the source.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
// Is this an SSA register use?
if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i)))
if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i))) {
// If the operand is a vreg-vreg copy, it is always safe to replace the
// source value with the input operand.
if (DefInst->getOpcode() == X86::MOVrr8 ||
DefInst->getOpcode() == X86::MOVrr16 ||
DefInst->getOpcode() == X86::MOVrr32) {
// Don't propagate physical registers into PHI nodes...
if (MI->getOpcode() != X86::PHI ||
(DefInst->getOperand(1).isRegister() &&
MRegisterInfo::isVirtualRegister(DefInst->getOperand(1).getReg())))
Changed = Propagate(MI, i, DefInst, 1);
unsigned Source, Dest;
if (TII.isMoveInstr(*DefInst, Source, Dest)) {
// Don't propagate physical registers into any instructions.
if (DefInst->getOperand(1).isRegister() &&
MRegisterInfo::isVirtualRegister(Source)) {
MI->getOperand(i).setReg(Source);
Changed = true;
++NumPHMoves;
}
}
}
// Perform instruction specific optimizations.

25
lib/Target/X86/X86PeepholeOpt.cpp
View File

@ -15,6 +15,8 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "Support/Statistic.h"
#include "Support/STLExtras.h"
@ -23,6 +25,7 @@ using namespace llvm;
namespace {
Statistic<> NumPHOpts("x86-peephole",
"Number of peephole optimization performed");
Statistic<> NumPHMoves("x86-peephole", "Number of peephole moves folded");
struct PH : public MachineFunctionPass {
virtual bool runOnMachineFunction(MachineFunction &MF);
@ -449,22 +452,26 @@ bool SSAPH::PeepholeOptimize(MachineBasicBlock &MBB,
bool Changed = false;
const TargetInstrInfo &TII = MBB.getParent()->getTarget().getInstrInfo();
// Scan the operands of this instruction. If any operands are
// register-register copies, replace the operand with the source.
for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i)
// Is this an SSA register use?
if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i)))
if (MachineInstr *DefInst = getDefiningInst(MI->getOperand(i))) {
// If the operand is a vreg-vreg copy, it is always safe to replace the
// source value with the input operand.
if (DefInst->getOpcode() == X86::MOVrr8 ||
DefInst->getOpcode() == X86::MOVrr16 ||
DefInst->getOpcode() == X86::MOVrr32) {
// Don't propagate physical registers into PHI nodes...
if (MI->getOpcode() != X86::PHI ||
(DefInst->getOperand(1).isRegister() &&
MRegisterInfo::isVirtualRegister(DefInst->getOperand(1).getReg())))
Changed = Propagate(MI, i, DefInst, 1);
unsigned Source, Dest;
if (TII.isMoveInstr(*DefInst, Source, Dest)) {
// Don't propagate physical registers into any instructions.
if (DefInst->getOperand(1).isRegister() &&
MRegisterInfo::isVirtualRegister(Source)) {
MI->getOperand(i).setReg(Source);
Changed = true;
++NumPHMoves;
}
}
}
// Perform instruction specific optimizations.