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Fix bug in zero-extending of shorts.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12453 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Brian Gaeke 2004-03-16 22:45:42 +00:00
parent 032f80fbf1
commit 6d339f9000
4 changed files with 8 additions and 8 deletions
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4
lib/Target/Sparc/InstSelectSimple.cpp
View File

@ -289,8 +289,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
} else { // add ushort
unsigned TmpReg = makeAnotherReg (I.getType ());
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (24);
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
}
break;
case cInt:

4
lib/Target/Sparc/SparcV8ISelSimple.cpp
View File

@ -289,8 +289,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
} else { // add ushort
unsigned TmpReg = makeAnotherReg (I.getType ());
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (24);
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
}
break;
case cInt:

4
lib/Target/SparcV8/InstSelectSimple.cpp
View File

@ -289,8 +289,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
} else { // add ushort
unsigned TmpReg = makeAnotherReg (I.getType ());
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (24);
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
}
break;
case cInt:

4
lib/Target/SparcV8/SparcV8ISelSimple.cpp
View File

@ -289,8 +289,8 @@ void V8ISel::visitBinaryOperator (BinaryOperator &I) {
BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
} else { // add ushort
unsigned TmpReg = makeAnotherReg (I.getType ());
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (24);
BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
}
break;
case cInt: