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Fix assembly syntax for AVX512 vector blend instructions.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@196393 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Cameron McInally 2013-12-04 18:05:36 +00:00
parent 3ddd790df1
commit 6d3d93c40b
2 changed files with 11 additions and 2 deletions
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4
lib/Target/X86/X86InstrAVX512.td
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@ -627,14 +627,14 @@ multiclass avx512_blendmask<bits<8> opc, string OpcodeStr, Intrinsic Int,
def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
(ins KRC:$mask, RC:$src1, x86memop:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
[]>,
EVEX_4V, EVEX_K;
def rm_Int : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
(ins KRC:$mask, RC:$src1, x86memop:$src2),
!strconcat(OpcodeStr,
"\t{$src2, $src1, $mask, $dst|$dst, $mask, $src1, $src2}"),
"\t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
[(set RC:$dst, (Int KRC:$mask, (vt RC:$src1),
(mem_frag addr:$src2)))]>,
EVEX_4V, EVEX_K;

9
test/CodeGen/X86/avx512-intrinsics.ll
View File

@ -355,6 +355,15 @@ define <8 x double> @test_x86_mskblend_pd_512(i8 %a0, <8 x double> %a1, <8 x dou
%res = call <8 x double> @llvm.x86.avx512.mskblend.pd.512(<8 x i1> %m0, <8 x double> %a1, <8 x double> %a2) ; <<8 x double>> [#uses=1]
ret <8 x double> %res
}
define <8 x double> @test_x86_mskblend_pd_512_memop(<8 x double> %a, <8 x double>* %ptr, i8 %mask) {
; CHECK-LABEL: test_x86_mskblend_pd_512_memop
; CHECK: vblendmpd {{.*}}, {{%zmm[0-9]}}, {{%zmm[0-9]}} {%k1}
%vmask = bitcast i8 %mask to <8 x i1>
%b = load <8 x double>* %ptr
%res = call <8 x double> @llvm.x86.avx512.mskblend.pd.512(<8 x i1> %vmask, <8 x double> %a, <8 x double> %b) ; <<8 x double>> [#uses=1]
ret <8 x double> %res
}
declare <8 x double> @llvm.x86.avx512.mskblend.pd.512(<8 x i1> %a0, <8 x double> %a1, <8 x double> %a2) nounwind readonly
define <16 x i32> @test_x86_mskblend_d_512(i16 %a0, <16 x i32> %a1, <16 x i32> %a2) {