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[mips] Set isAllocatable and CoveredBySubRegs.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189430 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka 2013-08-28 00:34:17 +00:00
parent c3e9457f6d
commit 6d55dfaf91
1 changed files with 3 additions and 1 deletions
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4
lib/Target/Mips/MipsRegisterInfo.td
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@ -60,6 +60,7 @@ class AFPR<bits<16> Enc, string n, list<Register> subregs>
class AFPR64<bits<16> Enc, string n, list<Register> subregs>
: MipsRegWithSubRegs<Enc, n, subregs> {
let SubRegIndices = [sub_lo, sub_hi];
let CoveredBySubRegs = 1;
}
// Mips 128-bit (aliased) MSA Registers
@ -294,7 +295,8 @@ def CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable;
// * FGR32 - 32 32-bit registers (single float only mode)
def FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>;
def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>;
def FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>,
Unallocatable;
def AFGR64 : RegisterClass<"Mips", [f64], 64, (add
// Return Values and Arguments