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Add new getOperandType(i) method to MachineInstr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@4330 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -238,14 +238,6 @@ public:
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//
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unsigned getNumOperands() const { return operands.size(); }
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bool operandIsDefined(unsigned i) const {
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return getOperand(i).opIsDef();
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}
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bool operandIsDefinedAndUsed(unsigned i) const {
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return getOperand(i).opIsDefAndUse();
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}
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const MachineOperand& getOperand(unsigned i) const {
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assert(i < operands.size() && "getOperand() out of range!");
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return operands[i];
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@ -254,6 +246,18 @@ public:
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assert(i < operands.size() && "getOperand() out of range!");
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return operands[i];
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}
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MachineOperand::MachineOperandType getOperandType(unsigned i) const {
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return getOperand(i).getOperandType();
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}
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bool operandIsDefined(unsigned i) const {
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return getOperand(i).opIsDef();
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}
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bool operandIsDefinedAndUsed(unsigned i) const {
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return getOperand(i).opIsDefAndUse();
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}
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//
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// Information about implicit operands of the instruction
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@ -339,7 +343,7 @@ public:
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// physical register after register allocation is complete.
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//
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void SetRegForOperand(unsigned i, int regNum);
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//
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// Iterator to enumerate machine operands.
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//
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@ -348,10 +352,10 @@ public:
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unsigned i;
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MITy MI;
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inline void skipToNextVal() {
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void skipToNextVal() {
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while (i < MI->getNumOperands() &&
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!((MI->getOperand(i).getOperandType() == MachineOperand::MO_VirtualRegister ||
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MI->getOperand(i).getOperandType() == MachineOperand::MO_CCRegister)
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!((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
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MI->getOperandType(i) == MachineOperand::MO_CCRegister)
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&& MI->getOperand(i).getVRegValue() != 0))
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++i;
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}
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