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Fix a few small typos I noticed when converting this over to the DAG->DAG

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selector.  Also, there is no difference between addSImm and addImm, so just
use addImm, folding some branches.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22819 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2005-08-17 01:25:14 +00:00
parent a033b4d8eb
commit 6d9aed4f8f
1 changed files with 11 additions and 12 deletions
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23
lib/Target/PowerPC/PPCISelPattern.cpp
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@ -36,14 +36,15 @@
using namespace llvm; using namespace llvm;
namespace { namespace {
Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted"); Statistic<> Recorded("ppc-codegen", "Number of recording ops emitted");
Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations"); Statistic<> FusedFP ("ppc-codegen", "Number of fused fp operations");
Statistic<>FrameOff("ppc-codegen", "Number of frame idx offsets collapsed"); Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
/// ISel - PPC32 specific code to select PPC32 machine instructions for // ISel - PPC32 specific code to select PPC32 machine instructions for
/// SelectionDAG operations. // SelectionDAG operations.
//===--------------------------------------------------------------------===// //===--------------------------------------------------------------------===//
class ISel : public SelectionDAGISel { class ISel : public SelectionDAGISel {
PPC32TargetLowering PPC32Lowering; PPC32TargetLowering PPC32Lowering;
SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
@ -764,7 +765,7 @@ bool ISel::SelectIntImmediateExpr(SDOperand N, unsigned Result,
// exit if not a constant // exit if not a constant
if (!CN) return false; if (!CN) return false;
// extract immediate // extract immediate
unsigned C = (unsigned)CN->getSignExtended(); unsigned C = (unsigned)CN->getValue();
// negate if required (ISD::SUB) // negate if required (ISD::SUB)
if (Negate) C = -C; if (Negate) C = -C;
// get the hi and lo portions of constant // get the hi and lo portions of constant
@ -784,17 +785,15 @@ bool ISel::SelectIntImmediateExpr(SDOperand N, unsigned Result,
unsigned Opr0 = SelectExpr(N.getOperand(0)); unsigned Opr0 = SelectExpr(N.getOperand(0));
// is a lo instruction needed // is a lo instruction needed
if (Lo) { if (Lo) {
// generate instruction for hi portion // generate instruction for lo portion
const MachineInstrBuilder &MIBLo = BuildMI(BB, OCLo, 2, Tmp).addReg(Opr0); BuildMI(BB, OCLo, 2, Tmp).addReg(Opr0).addImm(Lo);
if (IsArithmetic) MIBLo.addSImm(Lo); else MIBLo.addImm(Lo);
// need to switch out first operand for hi instruction // need to switch out first operand for hi instruction
Opr0 = Tmp; Opr0 = Tmp;
} }
// is a ho instruction needed // is a hi instruction needed
if (Hi) { if (Hi) {
// generate instruction for hi portion // generate instruction for hi portion
const MachineInstrBuilder &MIBHi = BuildMI(BB, OCHi, 2, Result).addReg(Opr0); BuildMI(BB, OCHi, 2, Result).addReg(Opr0).addImm(Hi);
if (IsArithmetic) MIBHi.addSImm(Hi); else MIBHi.addImm(Hi);
} }
return true; return true;
} }