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[PowerPC] VSX loads and stores support unaligned access
I've not yet updated PPCTTI because I'm not sure what the actual relative cost is compared to the aligned uses. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204848 91177308-0d34-0410-b5e6-96231b3b80d8
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@@ -7960,7 +7960,6 @@ SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
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unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
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unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
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if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
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if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
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TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
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TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
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// FIXME: Update this for VSX!
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(VT == MVT::v16i8 || VT == MVT::v8i16 ||
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(VT == MVT::v16i8 || VT == MVT::v8i16 ||
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VT == MVT::v4i32 || VT == MVT::v4f32) &&
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VT == MVT::v4i32 || VT == MVT::v4f32) &&
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LD->getAlignment() < ABIAlignment) {
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LD->getAlignment() < ABIAlignment) {
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@@ -8716,8 +8715,14 @@ bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
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if (!VT.isSimple())
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if (!VT.isSimple())
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return false;
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return false;
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if (VT.getSimpleVT().isVector())
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if (VT.getSimpleVT().isVector()) {
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if (PPCSubTarget.hasVSX()) {
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if (VT != MVT::v2f64 && VT != MVT::v2i64)
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return false;
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return false;
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} else {
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return false;
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}
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}
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if (VT == MVT::ppcf128)
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if (VT == MVT::ppcf128)
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return false;
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return false;
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@@ -244,6 +244,8 @@ unsigned PPCTTI::getMemoryOpCost(unsigned Opcode, Type *Src, unsigned Alignment,
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// Each load/store unit costs 1.
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// Each load/store unit costs 1.
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unsigned Cost = LT.first * 1;
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unsigned Cost = LT.first * 1;
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// FIXME: Update this for VSX loads/stores that support unaligned access.
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// PPC in general does not support unaligned loads and stores. They'll need
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// PPC in general does not support unaligned loads and stores. They'll need
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// to be decomposed based on the alignment factor.
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// to be decomposed based on the alignment factor.
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unsigned SrcBytes = LT.second.getStoreSize();
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unsigned SrcBytes = LT.second.getStoreSize();
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@@ -314,6 +314,24 @@ define void @test29(<2 x double>* %a, <2 x double> %b) {
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; CHECK: blr
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; CHECK: blr
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}
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}
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define <2 x double> @test28u(<2 x double>* %a) {
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%v = load <2 x double>* %a, align 8
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ret <2 x double> %v
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; CHECK-LABEL: @test28u
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; CHECK: lxvd2x 34, 0, 3
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; CHECK: blr
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}
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define void @test29u(<2 x double>* %a, <2 x double> %b) {
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store <2 x double> %b, <2 x double>* %a, align 8
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ret void
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; CHECK-LABEL: @test29u
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; CHECK: stxvd2x 34, 0, 3
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; CHECK: blr
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}
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define <2 x i64> @test30(<2 x i64>* %a) {
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define <2 x i64> @test30(<2 x i64>* %a) {
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%v = load <2 x i64>* %a, align 16
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%v = load <2 x i64>* %a, align 16
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ret <2 x i64> %v
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ret <2 x i64> %v
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