mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-02-12 18:33:22 +00:00
Fix whitespace and function names to be coding standardy.
No functional change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166814 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
f4a5a613fa
commit
6db893660f
@ -60,114 +60,114 @@ STATISTIC(NumReSchedUps, "Number of instructions re-scheduled up");
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STATISTIC(NumReSchedDowns, "Number of instructions re-scheduled down");
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namespace {
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class TwoAddressInstructionPass : public MachineFunctionPass {
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const InstrItineraryData *InstrItins;
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MachineRegisterInfo *MRI;
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LiveVariables *LV;
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SlotIndexes *Indexes;
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LiveIntervals *LIS;
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AliasAnalysis *AA;
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CodeGenOpt::Level OptLevel;
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class TwoAddressInstructionPass : public MachineFunctionPass {
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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const InstrItineraryData *InstrItins;
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MachineRegisterInfo *MRI;
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LiveVariables *LV;
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SlotIndexes *Indexes;
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LiveIntervals *LIS;
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AliasAnalysis *AA;
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CodeGenOpt::Level OptLevel;
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// DistanceMap - Keep track the distance of a MI from the start of the
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// current basic block.
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DenseMap<MachineInstr*, unsigned> DistanceMap;
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// DistanceMap - Keep track the distance of a MI from the start of the
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// current basic block.
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DenseMap<MachineInstr*, unsigned> DistanceMap;
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// SrcRegMap - A map from virtual registers to physical registers which
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// are likely targets to be coalesced to due to copies from physical
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// registers to virtual registers. e.g. v1024 = move r0.
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DenseMap<unsigned, unsigned> SrcRegMap;
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// SrcRegMap - A map from virtual registers to physical registers which are
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// likely targets to be coalesced to due to copies from physical registers to
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// virtual registers. e.g. v1024 = move r0.
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DenseMap<unsigned, unsigned> SrcRegMap;
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// DstRegMap - A map from virtual registers to physical registers which
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// are likely targets to be coalesced to due to copies to physical
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// registers from virtual registers. e.g. r1 = move v1024.
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DenseMap<unsigned, unsigned> DstRegMap;
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// DstRegMap - A map from virtual registers to physical registers which are
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// likely targets to be coalesced to due to copies to physical registers from
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// virtual registers. e.g. r1 = move v1024.
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DenseMap<unsigned, unsigned> DstRegMap;
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/// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
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/// during the initial walk of the machine function.
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SmallVector<MachineInstr*, 16> RegSequences;
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/// RegSequences - Keep track the list of REG_SEQUENCE instructions seen
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/// during the initial walk of the machine function.
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SmallVector<MachineInstr*, 16> RegSequences;
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bool Sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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bool sink3AddrInstruction(MachineBasicBlock *MBB, MachineInstr *MI,
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unsigned Reg,
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MachineBasicBlock::iterator OldPos);
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bool NoUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
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unsigned &LastDef);
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bool noUseAfterLastDef(unsigned Reg, MachineBasicBlock *MBB, unsigned Dist,
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unsigned &LastDef);
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bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
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MachineInstr *MI, MachineBasicBlock *MBB,
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unsigned Dist);
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bool isProfitableToCommute(unsigned regA, unsigned regB, unsigned regC,
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MachineInstr *MI, MachineBasicBlock *MBB,
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unsigned Dist);
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bool CommuteInstruction(MachineBasicBlock::iterator &mi,
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MachineFunction::iterator &mbbi,
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unsigned RegB, unsigned RegC, unsigned Dist);
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bool commuteInstruction(MachineBasicBlock::iterator &mi,
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MachineFunction::iterator &mbbi,
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unsigned RegB, unsigned RegC, unsigned Dist);
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bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
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bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
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bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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MachineFunction::iterator &mbbi,
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unsigned RegA, unsigned RegB, unsigned Dist);
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bool convertInstTo3Addr(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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MachineFunction::iterator &mbbi,
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unsigned RegA, unsigned RegB, unsigned Dist);
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bool isDefTooClose(unsigned Reg, unsigned Dist,
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MachineInstr *MI, MachineBasicBlock *MBB);
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bool isDefTooClose(unsigned Reg, unsigned Dist,
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MachineInstr *MI, MachineBasicBlock *MBB);
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bool RescheduleMIBelowKill(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &mi,
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bool rescheduleMIBelowKill(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg);
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bool rescheduleKillAboveMI(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg);
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bool tryInstructionTransform(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg);
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bool RescheduleKillAboveMI(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg);
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MachineFunction::iterator &mbbi,
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unsigned SrcIdx, unsigned DstIdx,
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unsigned Dist,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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bool TryInstructionTransform(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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MachineFunction::iterator &mbbi,
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unsigned SrcIdx, unsigned DstIdx,
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unsigned Dist,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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void scanUses(unsigned DstReg, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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void processCopy(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed);
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typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
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typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
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bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
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void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
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typedef SmallVector<std::pair<unsigned, unsigned>, 4> TiedPairList;
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typedef SmallDenseMap<unsigned, TiedPairList> TiedOperandMap;
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bool collectTiedOperands(MachineInstr *MI, TiedOperandMap&);
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void processTiedPairs(MachineInstr *MI, TiedPairList&, unsigned &Dist);
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/// eliminateRegSequences - Eliminate REG_SEQUENCE instructions as part of
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/// the de-ssa process. This replaces sources of REG_SEQUENCE as sub-register
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/// references of the register defined by REG_SEQUENCE.
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bool eliminateRegSequences();
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/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
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/// of the de-ssa process. This replaces sources of REG_SEQUENCE as
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/// sub-register references of the register defined by REG_SEQUENCE.
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bool EliminateRegSequences();
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public:
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static char ID; // Pass identification, replacement for typeid
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TwoAddressInstructionPass() : MachineFunctionPass(ID) {
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initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
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}
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public:
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static char ID; // Pass identification, replacement for typeid
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TwoAddressInstructionPass() : MachineFunctionPass(ID) {
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initializeTwoAddressInstructionPassPass(*PassRegistry::getPassRegistry());
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<LiveVariables>();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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AU.addRequired<AliasAnalysis>();
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AU.addPreserved<LiveVariables>();
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AU.addPreserved<SlotIndexes>();
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AU.addPreserved<LiveIntervals>();
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AU.addPreservedID(MachineLoopInfoID);
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AU.addPreservedID(MachineDominatorsID);
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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/// runOnMachineFunction - Pass entry point.
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bool runOnMachineFunction(MachineFunction&);
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};
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}
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/// runOnMachineFunction - Pass entry point.
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bool runOnMachineFunction(MachineFunction&);
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};
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} // end anonymous namespace
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char TwoAddressInstructionPass::ID = 0;
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INITIALIZE_PASS_BEGIN(TwoAddressInstructionPass, "twoaddressinstruction",
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@ -178,11 +178,11 @@ INITIALIZE_PASS_END(TwoAddressInstructionPass, "twoaddressinstruction",
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char &llvm::TwoAddressInstructionPassID = TwoAddressInstructionPass::ID;
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/// Sink3AddrInstruction - A two-address instruction has been converted to a
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/// sink3AddrInstruction - A two-address instruction has been converted to a
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/// three-address instruction to avoid clobbering a register. Try to sink it
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/// past the instruction that would kill the above mentioned register to reduce
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/// register pressure.
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bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
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bool TwoAddressInstructionPass::sink3AddrInstruction(MachineBasicBlock *MBB,
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MachineInstr *MI, unsigned SavedReg,
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MachineBasicBlock::iterator OldPos) {
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// FIXME: Shouldn't we be trying to do this before we three-addressify the
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@ -297,13 +297,14 @@ bool TwoAddressInstructionPass::Sink3AddrInstruction(MachineBasicBlock *MBB,
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return true;
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}
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/// NoUseAfterLastDef - Return true if there are no intervening uses between the
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/// noUseAfterLastDef - Return true if there are no intervening uses between the
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/// last instruction in the MBB that defines the specified register and the
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/// two-address instruction which is being processed. It also returns the last
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/// def location by reference
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bool TwoAddressInstructionPass::NoUseAfterLastDef(unsigned Reg,
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MachineBasicBlock *MBB, unsigned Dist,
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unsigned &LastDef) {
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bool TwoAddressInstructionPass::noUseAfterLastDef(unsigned Reg,
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MachineBasicBlock *MBB,
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unsigned Dist,
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unsigned &LastDef) {
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LastDef = 0;
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unsigned LastUse = Dist;
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for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(Reg),
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@ -514,13 +515,13 @@ TwoAddressInstructionPass::isProfitableToCommute(unsigned regA, unsigned regB,
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// If there is a use of regC between its last def (could be livein) and this
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// instruction, then bail.
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unsigned LastDefC = 0;
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if (!NoUseAfterLastDef(regC, MBB, Dist, LastDefC))
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if (!noUseAfterLastDef(regC, MBB, Dist, LastDefC))
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return false;
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// If there is a use of regB between its last def (could be livein) and this
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// instruction, then go ahead and make this transformation.
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unsigned LastDefB = 0;
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if (!NoUseAfterLastDef(regB, MBB, Dist, LastDefB))
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if (!noUseAfterLastDef(regB, MBB, Dist, LastDefB))
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return true;
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// Since there are no intervening uses for both registers, then commute
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@ -528,11 +529,11 @@ TwoAddressInstructionPass::isProfitableToCommute(unsigned regA, unsigned regB,
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return LastDefB && LastDefC && LastDefC > LastDefB;
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}
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/// CommuteInstruction - Commute a two-address instruction and update the basic
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/// commuteInstruction - Commute a two-address instruction and update the basic
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/// block, distance map, and live variables if needed. Return true if it is
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/// successful.
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bool
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TwoAddressInstructionPass::CommuteInstruction(MachineBasicBlock::iterator &mi,
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TwoAddressInstructionPass::commuteInstruction(MachineBasicBlock::iterator &mi,
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MachineFunction::iterator &mbbi,
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unsigned RegB, unsigned RegC, unsigned Dist) {
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MachineInstr *MI = mi;
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@ -586,10 +587,10 @@ TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
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return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
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}
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/// ConvertInstTo3Addr - Convert the specified two-address instruction into a
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/// convertInstTo3Addr - Convert the specified two-address instruction into a
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/// three address one. Return true if this transformation was successful.
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bool
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TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
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TwoAddressInstructionPass::convertInstTo3Addr(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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MachineFunction::iterator &mbbi,
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unsigned RegA, unsigned RegB,
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@ -607,7 +608,7 @@ TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
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// FIXME: Temporary workaround. If the new instruction doesn't
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// uses RegB, convertToThreeAddress must have created more
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// then one instruction.
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Sunk = Sink3AddrInstruction(mbbi, NewMI, RegB, mi);
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Sunk = sink3AddrInstruction(mbbi, NewMI, RegB, mi);
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mbbi->erase(mi); // Nuke the old inst.
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@ -626,10 +627,10 @@ TwoAddressInstructionPass::ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
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return false;
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}
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/// ScanUses - Scan forward recursively for only uses, update maps if the use
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/// scanUses - Scan forward recursively for only uses, update maps if the use
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/// is a copy or a two-address instruction.
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void
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TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
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TwoAddressInstructionPass::scanUses(unsigned DstReg, MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed) {
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SmallVector<unsigned, 4> VirtRegPairs;
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bool IsDstPhys;
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@ -674,7 +675,7 @@ TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
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}
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}
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/// ProcessCopy - If the specified instruction is not yet processed, process it
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/// processCopy - If the specified instruction is not yet processed, process it
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/// if it's a copy. For a copy instruction, we find the physical registers the
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/// source and destination registers might be mapped to. These are kept in
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/// point-to maps used to determine future optimizations. e.g.
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@ -686,7 +687,7 @@ TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
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/// coalesced to r0 (from the input side). v1025 is mapped to r1. v1026 is
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/// potentially joined with r1 on the output side. It's worthwhile to commute
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/// 'add' to eliminate a copy.
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void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
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void TwoAddressInstructionPass::processCopy(MachineInstr *MI,
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MachineBasicBlock *MBB,
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SmallPtrSet<MachineInstr*, 8> &Processed) {
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if (Processed.count(MI))
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@ -705,21 +706,21 @@ void TwoAddressInstructionPass::ProcessCopy(MachineInstr *MI,
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assert(SrcRegMap[DstReg] == SrcReg &&
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"Can't map to two src physical registers!");
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ScanUses(DstReg, MBB, Processed);
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scanUses(DstReg, MBB, Processed);
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}
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Processed.insert(MI);
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return;
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}
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/// RescheduleMIBelowKill - If there is one more local instruction that reads
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/// rescheduleMIBelowKill - If there is one more local instruction that reads
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/// 'Reg' and it kills 'Reg, consider moving the instruction below the kill
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/// instruction in order to eliminate the need for the copy.
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bool
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TwoAddressInstructionPass::RescheduleMIBelowKill(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg) {
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bool TwoAddressInstructionPass::
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rescheduleMIBelowKill(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg) {
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// Bail immediately if we don't have LV available. We use it to find kills
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// efficiently.
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if (!LV)
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@ -871,15 +872,15 @@ bool TwoAddressInstructionPass::isDefTooClose(unsigned Reg, unsigned Dist,
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return false;
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}
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/// RescheduleKillAboveMI - If there is one more local instruction that reads
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/// rescheduleKillAboveMI - If there is one more local instruction that reads
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/// 'Reg' and it kills 'Reg, consider moving the kill instruction above the
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/// current two-address instruction in order to eliminate the need for the
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/// copy.
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bool
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TwoAddressInstructionPass::RescheduleKillAboveMI(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg) {
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bool TwoAddressInstructionPass::
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rescheduleKillAboveMI(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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unsigned Reg) {
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// Bail immediately if we don't have LV available. We use it to find kills
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// efficiently.
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if (!LV)
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@ -1004,14 +1005,14 @@ TwoAddressInstructionPass::RescheduleKillAboveMI(MachineBasicBlock *MBB,
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return true;
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}
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/// TryInstructionTransform - For the case where an instruction has a single
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/// tryInstructionTransform - For the case where an instruction has a single
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/// pair of tied register operands, attempt some transformations that may
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/// either eliminate the tied operands or improve the opportunities for
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/// coalescing away the register copy. Returns true if no copy needs to be
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/// inserted to untie mi's operands (either because they were untied, or
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/// because mi was rescheduled, and will be visited again later).
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bool TwoAddressInstructionPass::
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TryInstructionTransform(MachineBasicBlock::iterator &mi,
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tryInstructionTransform(MachineBasicBlock::iterator &mi,
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MachineBasicBlock::iterator &nmi,
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MachineFunction::iterator &mbbi,
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unsigned SrcIdx, unsigned DstIdx, unsigned Dist,
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@ -1028,7 +1029,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
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bool regBKilled = isKilled(MI, regB, MRI, TII);
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if (TargetRegisterInfo::isVirtualRegister(regA))
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ScanUses(regA, &*mbbi, Processed);
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scanUses(regA, &*mbbi, Processed);
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// Check if it is profitable to commute the operands.
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unsigned SrcOp1, SrcOp2;
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@ -1057,7 +1058,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
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}
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// If it's profitable to commute, try to do so.
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if (TryCommute && CommuteInstruction(mi, mbbi, regB, regC, Dist)) {
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if (TryCommute && commuteInstruction(mi, mbbi, regB, regC, Dist)) {
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++NumCommuted;
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if (AggressiveCommute)
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++NumAggrCommuted;
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@ -1066,7 +1067,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
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// If there is one more use of regB later in the same MBB, consider
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// re-schedule this MI below it.
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if (RescheduleMIBelowKill(mbbi, mi, nmi, regB)) {
|
||||
if (rescheduleMIBelowKill(mbbi, mi, nmi, regB)) {
|
||||
++NumReSchedDowns;
|
||||
return true;
|
||||
}
|
||||
@ -1076,7 +1077,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
|
||||
// three-address instruction. Check if it is profitable.
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||||
if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
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||||
// Try to convert it.
|
||||
if (ConvertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) {
|
||||
if (convertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) {
|
||||
++NumConvertedTo3Addr;
|
||||
return true; // Done with this instruction.
|
||||
}
|
||||
@ -1085,7 +1086,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
|
||||
|
||||
// If there is one more use of regB later in the same MBB, consider
|
||||
// re-schedule it before this MI if it's legal.
|
||||
if (RescheduleKillAboveMI(mbbi, mi, nmi, regB)) {
|
||||
if (rescheduleKillAboveMI(mbbi, mi, nmi, regB)) {
|
||||
++NumReSchedUps;
|
||||
return true;
|
||||
}
|
||||
@ -1140,7 +1141,7 @@ TryInstructionTransform(MachineBasicBlock::iterator &mi,
|
||||
unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB);
|
||||
MachineBasicBlock::iterator NewMI = NewMIs[1];
|
||||
bool TransformSuccess =
|
||||
TryInstructionTransform(NewMI, mi, mbbi,
|
||||
tryInstructionTransform(NewMI, mi, mbbi,
|
||||
NewSrcIdx, NewDstIdx, Dist, Processed);
|
||||
if (TransformSuccess ||
|
||||
NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
|
||||
@ -1399,7 +1400,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
|
||||
|
||||
DistanceMap.insert(std::make_pair(mi, ++Dist));
|
||||
|
||||
ProcessCopy(&*mi, &*mbbi, Processed);
|
||||
processCopy(&*mi, &*mbbi, Processed);
|
||||
|
||||
// First scan through all the tied register uses in this instruction
|
||||
// and record a list of pairs of tied operands for each register.
|
||||
@ -1424,7 +1425,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
|
||||
unsigned SrcReg = mi->getOperand(SrcIdx).getReg();
|
||||
unsigned DstReg = mi->getOperand(DstIdx).getReg();
|
||||
if (SrcReg != DstReg &&
|
||||
TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist,
|
||||
tryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist,
|
||||
Processed)) {
|
||||
// The tied operands have been eliminated or shifted further down the
|
||||
// block to ease elimination. Continue processing with 'nmi'.
|
||||
@ -1465,7 +1466,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &Func) {
|
||||
|
||||
// Eliminate REG_SEQUENCE instructions. Their whole purpose was to preseve
|
||||
// SSA form. It's now safe to de-SSA.
|
||||
MadeChange |= EliminateRegSequences();
|
||||
MadeChange |= eliminateRegSequences();
|
||||
|
||||
return MadeChange;
|
||||
}
|
||||
@ -1523,7 +1524,7 @@ static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
|
||||
return false;
|
||||
}
|
||||
|
||||
/// EliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
|
||||
/// eliminateRegSequences - Eliminate REG_SEQUENCE instructions as part
|
||||
/// of the de-ssa process. This replaces sources of REG_SEQUENCE as
|
||||
/// sub-register references of the register defined by REG_SEQUENCE. e.g.
|
||||
///
|
||||
@ -1531,7 +1532,7 @@ static bool HasOtherRegSequenceUses(unsigned Reg, MachineInstr *RegSeq,
|
||||
/// %reg1031<def> = REG_SEQUENCE %reg1029<kill>, 5, %reg1030<kill>, 6
|
||||
/// =>
|
||||
/// %reg1031:5<def>, %reg1031:6<def> = VLD1q16 %reg1024<kill>, ...
|
||||
bool TwoAddressInstructionPass::EliminateRegSequences() {
|
||||
bool TwoAddressInstructionPass::eliminateRegSequences() {
|
||||
if (RegSequences.empty())
|
||||
return false;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user