Port more assembler tests over to disassembler tests, and fix a minor logic error that exposed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139240 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

@@ -2786,7 +2786,7 @@ DecodeThumb2BCCInstruction(llvm::MCInst &Inst, unsigned Insn,
         break;
       case 0xf3bf8f6:
         Inst.setOpcode(ARM::t2ISB);
-        return MCDisassembler::Success;
+        break;
     }
 
     unsigned imm = fieldFromInstruction32(Insn, 0, 4);

test/MC/Disassembler/ARM/thumb2.txt

@@ -244,6 +244,164 @@
 0x1f 0xb9
 0x37 0xb9
 
+#------------------------------------------------------------------------------
+# CDP/CDP2
+#------------------------------------------------------------------------------
+# CHECK: cdp  p7, #1, c1, c1, c1, #4
+# CHECK: cdp2  p7, #1, c1, c1, c1, #4
+
+0x11 0xee 0x81 0x17
+0x11 0xfe 0x81 0x17
+
+
+#------------------------------------------------------------------------------
+# CLREX
+#------------------------------------------------------------------------------
+#CHECK: clrex
+#CHECK: it ne
+#CHECK: clrexne
+
+0xbf 0xf3 0x2f 0x8f
+0x18 0xbf
+0xbf 0xf3 0x2f 0x8f
+
+
+#------------------------------------------------------------------------------
+# CLZ
+#------------------------------------------------------------------------------
+#CHECK: clz r1, r2
+#CHECK: it eq
+#CHECK: clzeq r1, r2
+
+0xb2 0xfa 0x82 0xf1
+0x08 0xbf
+0xb2 0xfa 0x82 0xf1
+
+
+#------------------------------------------------------------------------------
+# CMN
+#------------------------------------------------------------------------------
+#CHECK: cmn.w r1, #15
+#CHECK: cmn.w r8, r6
+#CHECK: cmn.w r1, r6, lsl #10
+#CHECK: cmn.w r1, r6, lsr #10
+#CHECK: cmn.w sp, r6, lsr #10
+#CHECK: cmn.w r1, r6, asr #10
+#CHECK: cmn.w r1, r6, ror #10
+
+0x11 0xf1 0x0f 0x0f
+0x18 0xeb 0x06 0x0f
+0x11 0xeb 0x86 0x2f
+0x11 0xeb 0x96 0x2f
+0x1d 0xeb 0x96 0x2f
+0x11 0xeb 0xa6 0x2f
+0x11 0xeb 0xb6 0x2f
+
+
+#------------------------------------------------------------------------------
+# CMP
+#------------------------------------------------------------------------------
+#CHECK: cmp.w r5, #65280
+#CHECK: cmp.w r4, r12
+#CHECK: cmp.w r9, r6, lsl #12
+#CHECK: cmp.w r3, r7, lsr #31
+#CHECK: cmp.w sp, r6, lsr #1
+#CHECK: cmp.w r2, r5, asr #24
+#CHECK: cmp.w r1, r4, ror #15
+
+0xb5 0xf5 0x7f 0x4f
+0xb4 0xeb 0x0c 0x0f
+0xb9 0xeb 0x06 0x3f
+0xb3 0xeb 0xd7 0x7f
+0xbd 0xeb 0x56 0x0f
+0xb2 0xeb 0x25 0x6f
+0xb1 0xeb 0xf4 0x3f
+
+
+#------------------------------------------------------------------------------
+# DBG
+#------------------------------------------------------------------------------
+#CHECK: dbg #5
+#CHECK: dbg #0
+#CHECK: dbg #15
+
+0xaf 0xf3 0xf5 0x80
+0xaf 0xf3 0xf0 0x80
+0xaf 0xf3 0xff 0x80
+
+
+#------------------------------------------------------------------------------
+# DMB
+#------------------------------------------------------------------------------
+#CHECK: dmb sy
+#CHECK: dmb st
+#CHECK: dmb ish
+#CHECK: dmb ishst
+#CHECK: dmb nsh
+#CHECK: dmb nshst
+#CHECK: dmb osh
+#CHECK: dmb oshst
+#CHECK: dmb
+
+0xbf 0xf3 0x5f 0x8f
+0xbf 0xf3 0x5e 0x8f
+0xbf 0xf3 0x5b 0x8f
+0xbf 0xf3 0x5a 0x8f
+0xbf 0xf3 0x57 0x8f
+0xbf 0xf3 0x56 0x8f
+0xbf 0xf3 0x53 0x8f
+0xbf 0xf3 0x52 0x8f
+0xbf 0xf3 0x5f 0x8f
+
+
+#------------------------------------------------------------------------------
+# DSB
+#------------------------------------------------------------------------------
+#CHECK: dsb sy
+#CHECK: dsb st
+#CHECK: dsb ish
+#CHECK: dsb ishst
+#CHECK: dsb nsh
+#CHECK: dsb nshst
+#CHECK: dsb osh
+#CHECK: dsb oshst
+
+0xbf 0xf3 0x4f 0x8f
+0xbf 0xf3 0x4e 0x8f
+0xbf 0xf3 0x4b 0x8f
+0xbf 0xf3 0x4a 0x8f
+0xbf 0xf3 0x47 0x8f
+0xbf 0xf3 0x46 0x8f
+0xbf 0xf3 0x43 0x8f
+0xbf 0xf3 0x42 0x8f
+
+
+#------------------------------------------------------------------------------
+# EOR
+#------------------------------------------------------------------------------
+#CHECK: eor r4, r5, #61440
+#CHECK: eor.w r4, r5, r6
+#CHECK: eor.w r4, r5, r6, lsl #5
+#CHECK: eor.w r4, r5, r6, lsr #5
+#CHECK: eor.w r4, r5, r6, lsr #5
+#CHECK: eor.w r4, r5, r6, asr #5
+#CHECK: eor.w r4, r5, r6, ror #5
+
+0x85 0xf4 0x70 0x44
+0x85 0xea 0x06 0x04
+0x85 0xea 0x46 0x14
+0x85 0xea 0x56 0x14
+0x85 0xea 0x56 0x14
+0x85 0xea 0x66 0x14
+0x85 0xea 0x76 0x14
+
+
+#------------------------------------------------------------------------------
+# ISB
+#------------------------------------------------------------------------------
+#CHECK: isb sy
+
+0xbf 0xf3 0x6f 0x8f
 
 #------------------------------------------------------------------------------
 # IT