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Use the dwarf->llvm mapping to print register names in the cfi

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directives.

Fixes PR9826.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132317 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola 2011-05-30 20:20:15 +00:00
parent acbf107d9b
commit 6e032942cf
40 changed files with 183 additions and 26 deletions
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4
include/llvm/Target/TargetAsmInfo.h
View File

@ -95,6 +95,10 @@ public:
return TRI->getDwarfRegNum(RegNum, isEH);
}
int getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
return TRI->getLLVMRegNum(DwarfRegNum, isEH);
}
int getSEHRegNum(unsigned RegNum) const {
return TRI->getSEHRegNum(RegNum);
}

2
include/llvm/Target/TargetRegisterInfo.h
View File

@ -802,6 +802,8 @@ public:
/// debugging info.
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;
virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const = 0;
/// getFrameRegister - This method should return the register used as a base
/// for values allocated in the current stack frame.
virtual unsigned getFrameRegister(const MachineFunction &MF) const = 0;

30
lib/MC/MCAsmStreamer.cpp
View File

@ -54,6 +54,8 @@ class MCAsmStreamer : public MCStreamer {
bool needsSet(const MCExpr *Value);
void EmitRegisterName(int64_t Register);
public:
MCAsmStreamer(MCContext &Context, formatted_raw_ostream &os,
bool isVerboseAsm, bool useLoc, bool useCFI,
@ -819,13 +821,25 @@ void MCAsmStreamer::EmitCFIEndProc() {
EmitEOL();
}
void MCAsmStreamer::EmitRegisterName(int64_t Register) {
if (InstPrinter) {
const TargetAsmInfo &asmInfo = getContext().getTargetAsmInfo();
unsigned LLVMRegister = asmInfo.getLLVMRegNum(Register, true);
OS << '%' << InstPrinter->getRegName(LLVMRegister);
} else {
OS << Register;
}
}
void MCAsmStreamer::EmitCFIDefCfa(int64_t Register, int64_t Offset) {
MCStreamer::EmitCFIDefCfa(Register, Offset);
if (!UseCFI)
return;
OS << "\t.cfi_def_cfa " << Register << ", " << Offset;
OS << "\t.cfi_def_cfa ";
EmitRegisterName(Register);
OS << ", " << Offset;
EmitEOL();
}
@ -845,7 +859,8 @@ void MCAsmStreamer::EmitCFIDefCfaRegister(int64_t Register) {
if (!UseCFI)
return;
OS << "\t.cfi_def_cfa_register " << Register;
OS << "\t.cfi_def_cfa_register ";
EmitRegisterName(Register);
EmitEOL();
}
@ -855,7 +870,9 @@ void MCAsmStreamer::EmitCFIOffset(int64_t Register, int64_t Offset) {
if (!UseCFI)
return;
OS << "\t.cfi_offset " << Register << ", " << Offset;
OS << "\t.cfi_offset ";
EmitRegisterName(Register);
OS << ", " << Offset;
EmitEOL();
}
@ -906,7 +923,8 @@ void MCAsmStreamer::EmitCFISameValue(int64_t Register) {
if (!UseCFI)
return;
OS << "\t.cfi_same_value " << Register;
OS << "\t.cfi_same_value ";
EmitRegisterName(Register);
EmitEOL();
}
@ -916,7 +934,9 @@ void MCAsmStreamer::EmitCFIRelOffset(int64_t Register, int64_t Offset) {
if (!UseCFI)
return;
OS << "\t.cfi_rel_offset " << Register << ", " << Offset;
OS << "\t.cfi_rel_offset ";
EmitRegisterName(Register);
OS << ", " << Offset;
EmitEOL();
}

4
lib/Target/ARM/ARMBaseRegisterInfo.cpp
View File

@ -684,6 +684,10 @@ int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int ARMBaseRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return ARMGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
const MachineFunction &MF) const {
switch (Reg) {

1
lib/Target/ARM/ARMBaseRegisterInfo.h
View File

@ -172,6 +172,7 @@ public:
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
bool isLowRegister(unsigned Reg) const;

5
lib/Target/Alpha/AlphaRegisterInfo.cpp
View File

@ -199,6 +199,11 @@ int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return -1;
}
int AlphaRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum, bool isEH) const {
llvm_unreachable("What is the dwarf register number");
return -1;
}
#include "AlphaGenRegisterInfo.inc"
std::string AlphaRegisterInfo::getPrettyName(unsigned reg)

1
lib/Target/Alpha/AlphaRegisterInfo.h
View File

@ -48,6 +48,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
static std::string getPrettyName(unsigned reg);
};

6
lib/Target/Blackfin/BlackfinRegisterInfo.cpp
View File

@ -351,5 +351,11 @@ int BlackfinRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return -1;
}
int BlackfinRegisterInfo::getLLVMRegNum(unsigned DwarfRegNum,
bool isEH) const {
llvm_unreachable("What is the dwarf register number");
return -1;
}
#include "BlackfinGenRegisterInfo.inc"

1
lib/Target/Blackfin/BlackfinRegisterInfo.h
View File

@ -60,6 +60,7 @@ namespace llvm {
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
// Utility functions
void adjustRegister(MachineBasicBlock &MBB,

4
lib/Target/CellSPU/SPURegisterInfo.cpp
View File

@ -328,6 +328,10 @@ SPURegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return SPUGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int SPURegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
return SPUGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
}
int
SPURegisterInfo::convertDFormToXForm(int dFormOpcode) const
{

1
lib/Target/CellSPU/SPURegisterInfo.h
View File

@ -83,6 +83,7 @@ namespace llvm {
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
//! Convert D-form load/store to X-form load/store
/*!

4
lib/Target/MBlaze/MBlazeRegisterInfo.cpp
View File

@ -356,5 +356,9 @@ int MBlazeRegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
return MBlazeGenRegisterInfo::getDwarfRegNumFull(RegNo,0);
}
int MBlazeRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return MBlazeGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
#include "MBlazeGenRegisterInfo.inc"

1
lib/Target/MBlaze/MBlazeRegisterInfo.h
View File

@ -75,6 +75,7 @@ struct MBlazeRegisterInfo : public MBlazeGenRegisterInfo {
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

5
lib/Target/MSP430/MSP430RegisterInfo.cpp
View File

@ -242,4 +242,9 @@ int MSP430RegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return 0;
}
int MSP430RegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
llvm_unreachable("Not implemented yet!");
return 0;
}
#include "MSP430GenRegisterInfo.inc"

1
lib/Target/MSP430/MSP430RegisterInfo.h
View File

@ -61,6 +61,7 @@ public:
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

4
lib/Target/Mips/MipsRegisterInfo.cpp
View File

@ -278,4 +278,8 @@ getDwarfRegNum(unsigned RegNum, bool isEH) const {
return MipsGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int MipsRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return MipsGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
#include "MipsGenRegisterInfo.inc"

1
lib/Target/Mips/MipsRegisterInfo.h
View File

@ -63,6 +63,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

3
lib/Target/PTX/PTXRegisterInfo.h
View File

@ -57,6 +57,9 @@ struct PTXRegisterInfo : public PTXGenRegisterInfo {
virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const {
return PTXGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
virtual int getLLVMRegNum(unsigned RegNum, bool isEH) const {
return PTXGenRegisterInfo::getLLVMRegNumFull(RegNum, 0);
}
}; // struct PTXRegisterInfo
} // namespace llvm

3
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.cpp
View File

@ -26,6 +26,9 @@ StringRef PPCInstPrinter::getOpcodeName(unsigned Opcode) const {
return getInstructionName(Opcode);
}
StringRef PPCInstPrinter::getRegName(unsigned RegNo) const {
return getRegisterName(RegNo);
}
void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
// Check for slwi/srwi mnemonics.

1
lib/Target/PowerPC/InstPrinter/PPCInstPrinter.h
View File

@ -33,6 +33,7 @@ public:
return SyntaxVariant == 1;
}
StringRef getRegName(unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &O);
virtual StringRef getOpcodeName(unsigned Opcode) const;

8
lib/Target/PowerPC/PPCFrameLowering.cpp
View File

@ -487,6 +487,14 @@ void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
unsigned Reg = CSI[I].getReg();
if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
// This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
// subregisters of CR2. We just need to emit a move of CR2.
if (Reg == PPC::CR2LT || Reg == PPC::CR2GT || Reg == PPC::CR2EQ)
continue;
if (Reg == PPC::CR2UN)
Reg = PPC::CR2;
MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
MachineLocation CSSrc(Reg);
Moves.push_back(MachineMove(Label, CSDst, CSSrc));

8
lib/Target/PowerPC/PPCRegisterInfo.cpp
View File

@ -702,4 +702,12 @@ int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return PPCGenRegisterInfo::getDwarfRegNumFull(RegNum, Flavour);
}
int PPCRegisterInfo::getLLVMRegNum(unsigned RegNum, bool isEH) const {
// FIXME: Most probably dwarf numbers differs for Linux and Darwin
unsigned Flavour = Subtarget.isPPC64() ?
DWARFFlavour::PPC64 : DWARFFlavour::PPC32;
return PPCGenRegisterInfo::getLLVMRegNumFull(RegNum, Flavour);
}
#include "PPCGenRegisterInfo.inc"

1
lib/Target/PowerPC/PPCRegisterInfo.h
View File

@ -68,6 +68,7 @@ public:
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

4
lib/Target/Sparc/SparcRegisterInfo.cpp
View File

@ -130,5 +130,9 @@ int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return SparcGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int SparcRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return SparcGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
#include "SparcGenRegisterInfo.inc"

1
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -52,6 +52,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

6
lib/Target/SystemZ/SystemZRegisterInfo.cpp
View File

@ -139,4 +139,10 @@ int SystemZRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return -1;
}
int SystemZRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
assert(0 && "What is the dwarf register number");
return -1;
}
#include "SystemZGenRegisterInfo.inc"

1
lib/Target/SystemZ/SystemZRegisterInfo.h
View File

@ -54,6 +54,7 @@ struct SystemZRegisterInfo : public SystemZGenRegisterInfo {
unsigned getEHHandlerRegister() const;
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

4
lib/Target/X86/InstPrinter/X86ATTInstPrinter.cpp
View File

@ -41,6 +41,10 @@ X86ATTInstPrinter::X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
&TM.getSubtarget<X86Subtarget>()));
}
StringRef X86ATTInstPrinter::getRegName(unsigned RegNo) const {
return getRegisterName(RegNo);
}
void X86ATTInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
// Try to print any aliases first.
if (!printAliasInstr(MI, OS))

1
lib/Target/X86/InstPrinter/X86ATTInstPrinter.h
View File

@ -26,6 +26,7 @@ class X86ATTInstPrinter : public MCInstPrinter {
public:
X86ATTInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI);
StringRef getRegName(unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &OS);
virtual StringRef getOpcodeName(unsigned Opcode) const;

4
lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp
View File

@ -29,6 +29,10 @@ using namespace llvm;
#define GET_INSTRUCTION_NAME
#include "X86GenAsmWriter1.inc"
StringRef X86IntelInstPrinter::getRegName(unsigned RegNo) const {
return getRegisterName(RegNo);
}
void X86IntelInstPrinter::printInst(const MCInst *MI, raw_ostream &OS) {
printInstruction(MI, OS);

1
lib/Target/X86/InstPrinter/X86IntelInstPrinter.h
View File

@ -27,6 +27,7 @@ public:
X86IntelInstPrinter(TargetMachine &TM, const MCAsmInfo &MAI)
: MCInstPrinter(MAI) {}
StringRef getRegName(unsigned RegNo) const;
virtual void printInst(const MCInst *MI, raw_ostream &OS);
virtual StringRef getOpcodeName(unsigned Opcode) const;

41
lib/Target/X86/X86RegisterInfo.cpp
View File

@ -73,29 +73,40 @@ X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
}
}
static unsigned getFlavour(const X86Subtarget *Subtarget, bool isEH) {
if (!Subtarget->is64Bit()) {
if (Subtarget->isTargetDarwin()) {
if (isEH)
return DWARFFlavour::X86_32_DarwinEH;
else
return DWARFFlavour::X86_32_Generic;
} else if (Subtarget->isTargetCygMing()) {
// Unsupported by now, just quick fallback
return DWARFFlavour::X86_32_Generic;
} else {
return DWARFFlavour::X86_32_Generic;
}
}
return DWARFFlavour::X86_64;
}
/// getDwarfRegNum - This function maps LLVM register identifiers to the DWARF
/// specific numbering, used in debug info and exception tables.
int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const {
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
unsigned Flavour = DWARFFlavour::X86_64;
if (!Subtarget->is64Bit()) {
if (Subtarget->isTargetDarwin()) {
if (isEH)
Flavour = DWARFFlavour::X86_32_DarwinEH;
else
Flavour = DWARFFlavour::X86_32_Generic;
} else if (Subtarget->isTargetCygMing()) {
// Unsupported by now, just quick fallback
Flavour = DWARFFlavour::X86_32_Generic;
} else {
Flavour = DWARFFlavour::X86_32_Generic;
}
}
unsigned Flavour = getFlavour(Subtarget, isEH);
return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
}
/// getLLVMRegNum - This function maps DWARF register numbers to LLVM register.
int X86RegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>();
unsigned Flavour = getFlavour(Subtarget, isEH);
return X86GenRegisterInfo::getLLVMRegNumFull(DwarfRegNo, Flavour);
}
int
X86RegisterInfo::getSEHRegNum(unsigned i) const {
int reg = getX86RegNum(i);

1
lib/Target/X86/X86RegisterInfo.h
View File

@ -80,6 +80,7 @@ public:
/// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum
/// (created by TableGen) for target dependencies.
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
// FIXME: This should be tablegen'd like getDwarfRegNum is
int getSEHRegNum(unsigned i) const;

4
lib/Target/XCore/XCoreRegisterInfo.cpp
View File

@ -315,6 +315,10 @@ int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
}
int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
}
unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();

1
lib/Target/XCore/XCoreRegisterInfo.h
View File

@ -75,6 +75,7 @@ public:
//! Get DWARF debugging register number
int getDwarfRegNum(unsigned RegNum, bool isEH) const;
int getLLVMRegNum(unsigned RegNum, bool isEH) const;
};
} // end namespace llvm

2
test/CodeGen/X86/2008-08-31-EH_RETURN32.ll
View File

@ -1,5 +1,5 @@
; Check that eh_return & unwind_init were properly lowered
; RUN: llc < %s | grep %ebp | count 7
; RUN: llc < %s | grep %ebp | count 9
; RUN: llc < %s | grep %ecx | count 5
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"

2
test/CodeGen/X86/2008-08-31-EH_RETURN64.ll
View File

@ -1,5 +1,5 @@
; Check that eh_return & unwind_init were properly lowered
; RUN: llc < %s | grep %rbp | count 5
; RUN: llc < %s | grep %rbp | count 7
; RUN: llc < %s | grep %rcx | count 3
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"

4
test/CodeGen/X86/empty-functions.ll
View File

@ -20,10 +20,10 @@ entry:
; CHECK-FP-NEXT: :
; CHECK-FP-NEXT: .cfi_def_cfa_offset 16
; CHECK-FP-NEXT: :
; CHECK-FP-NEXT: .cfi_offset 6, -16
; CHECK-FP-NEXT: .cfi_offset %rbp, -16
; CHECK-FP-NEXT: movq %rsp, %rbp
; CHECK-FP-NEXT: :
; CHECK-FP-NEXT: .cfi_def_cfa_register 6
; CHECK-FP-NEXT: .cfi_def_cfa_register %rbp
; CHECK-FP-NEXT: nop
; CHECK-FP-NEXT: :
; CHECK-FP-NEXT: .cfi_endproc

4
test/CodeGen/X86/pr9743.ll
View File

@ -9,9 +9,9 @@ define void @f() {
; CHECK-NEXT: :
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: :
; CHECK-NEXT: .cfi_offset 6, -16
; CHECK-NEXT: .cfi_offset %rbp, -16
; CHECK-NEXT: movq %rsp, %rbp
; CHECK-NEXT: :
; CHECK-NEXT: .cfi_def_cfa_register 6
; CHECK-NEXT: .cfi_def_cfa_register %rbp
; CHECK-NEXT: popq %rbp
; CHECK-NEXT: ret

29
utils/TableGen/RegisterInfoEmitter.cpp
View File

@ -80,6 +80,8 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " virtual int getDwarfRegNumFull(unsigned RegNum, "
<< "unsigned Flavour) const;\n"
<< " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
<< "unsigned Flavour) const;\n"
<< " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
<< " virtual bool needsStackRealignment(const MachineFunction &) const\n"
<< " { return false; }\n"
@ -989,6 +991,33 @@ void RegisterInfoEmitter::run(raw_ostream &OS) {
for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
I->second.push_back(-1);
// Emit reverse information about the dwarf register numbers.
OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
<< "unsigned Flavour) const {\n"
<< " switch (Flavour) {\n"
<< " default:\n"
<< " assert(0 && \"Unknown DWARF flavour\");\n"
<< " return -1;\n";
for (unsigned i = 0, e = maxLength; i != e; ++i) {
OS << " case " << i << ":\n"
<< " switch (DwarfRegNum) {\n"
<< " default:\n"
<< " assert(0 && \"Invalid DwarfRegNum\");\n"
<< " return -1;\n";
for (DwarfRegNumsMapTy::iterator
I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
int DwarfRegNo = I->second[i];
if (DwarfRegNo >= 0)
OS << " case " << DwarfRegNo << ":\n"
<< " return " << getQualifiedName(I->first) << ";\n";
}
OS << " };\n";
}
OS << " };\n}\n\n";
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *Reg = Regs[i].TheDef;
const RecordVal *V = Reg->getValue("DwarfAlias");